时序驱动的放置阶段遇到错误

您未能包含用于确定A4引脚不是具有时钟功能的I / O的部件和封装组合，但很可能就是这种情况。
“修复”它的唯一方法是使用错误消息中的说明。
这将导致使用较低性能的路由路径，并且不会保证I / O时序。
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以下为原文

You failed to include the part and package combination that you are using to confrim that the A4 pin is not a clock capable I/O, but that is very likely the case.
 
The only way to "fix" it is to use to follow the instructions in the error message. This will result in using a lower performance routing path and without guaranteeed I/O timing.
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这个问题是由时钟布局器的布局规划不良引起的。在14.1中有一个更具描述性的错误错误：位置：543  - 由于设计的复杂性和/或约束，这种设计不适合该设备中可用的切片数量
。按类型取代实例：LUT 136（0.9％）FF 100（3.1％）请评估以下内容：从该错误中，我们可以推断出有一个布局不佳的BUFG网络，只给设计一些时钟区域
放置组件。
应用约束将布局规划扩展到所有时钟区域并解决了问题。
时钟放置器给出时钟#AREA_GROUP“CLKAG_sys_clk”RANGE = CLOCKREGION_X0Y0，CLOCKREGION_X0Y1，CLOCKREGION_X1Y1，CLOCKREGION_X0Y2，CLOCKREGION_X0Y3，CLOCKREGION_X0Y4，CLOCKREGION_X1Y4，CLOCKREGION_X0Y5，CLOCKREGION_X0Y6，CLOCKREGION_X0Y7;
这是变通方法AREA_GROUP“CLKAG_sys_clk”RANGE = CLOCKREGION_X0Y0：CLOCKREGION_X1Y7;
由seema加入#added
谢谢和RegardsBalkrishan -----------------------------------------------
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以下为原文

The issue was caused by poor floorplanning by the clock placer.


In 14.1 there is a more descriptive error



ERROR:Place:543 - This design does not fit into the number of slices available in this device due to the complexity of
the design and/or constraints.

Unplaced instances by type:

LUT 136 (0.9%)
FF 100 (3.1%)

Please evaluate the following:



From that error , we are able to deduce that there is a BUFG net that is poorly floorplanned giving the design only a few clockregions to place the components.



Applied constraints that would expand the floorplanning to all the clockregions and that resolved the issue.




clock placer gave the clock


#AREA_GROUP "CLKAG_sys_clk" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X0Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;

This is the workaround

AREA_GROUP "CLKAG_sys_clk" RANGE = CLOCKREGION_X0Y0:CLOCKREGION_X1Y7; #added by seemaThanks and Regards
Balkrishan
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