包装：1654时序驱动的放置阶段遇到错误

当设备填满时，这种错误会更频繁地发生。
你可以看一下
综合报告末尾的资源使用综合估算
（.syr文件）或在“设计摘要”视图中。
有时候我有一些设计，其中地图会因某些起始成本表而失败
价值而不是其他。
您可以尝试从默认设置更改设置
（-t 1）到其他一些值（-t 2等）或尝试与SmartXplorer一起运行以查看是否
你可以解决这个问题。
HTH，
的Gabor
-  Gabor



以下为原文

This sort of error happens more often when the device fills up.  You can look at the
synthesis estimate of resource usage either at the end of the synthesis report
( .syr file) or in the Design Summary view.
 
Sometimes I have had designs where map will fail for some starting cost table
values and not others.  You could try changing the setting from the default
(-t 1) to some other value (-t 2, etc.) or try to run with SmartXplorer to see if
you can get past this  problem.
 
HTH,
 
Gabor
-- Gabor

当fitter在全局放置期间失败时，它应该打印Place：543错误，该错误列出了无法适应的组件。
在13.4中有一个回归，它有时无法打印该列表，这将使您对失败有所了解。
您可以尝试使用早期版本来查看是否获得了更好的错误消息或甚至可能成功运行。
我提到的错误处理错误已修复为14.1。



以下为原文

When the fitter fails during global placement, it is supposed to print a Place:543 error that lists the components that failed to fit. There was a regression in 13.4 where it sometimes fails to print that list which would give you some insight into the failure. You could try an earlier version to see if you get better error messaging or possibly even a successful run. The error handling bug I mentioned has been fixed for 14.1.

没有任何其他解释我有同样的错误。
我试图改变Map Process的设置，但没有结果。
ISE 13.2，Spartan6 LX9Phase 9.8全球定位（校验和：5342c8f3）实际时间：3分37秒相位10.9局部放置优化阶段10.9局部放置优化（校验和：79baba73）实际时间：3分钟37秒完成放置完成的总实时时间：3分钟
37秒完成Placer完成的总CPU时间：3分31秒ERROR：Pack：1654  - 时序驱动的放置阶段遇到错误。完成映射。有关详细信息，请参阅MAP报告文件“test_map.mrp”。在打包阶段遇到问题
.Design Summary --------------错误数：1警告数：1进程“Map”失败我该怎么办？



以下为原文

I have the same error without any other explanation. I have tried to change the settings of Map Process, but it was without result. ISE 13.2, Spartan6 LX9

Phase 9.8  Global Placement (Checksum:5342c8f3) REAL time: 3 mins 37 secs
Phase 10.9  Local Placement Optimization
Phase 10.9  Local Placement Optimization (Checksum:79baba73) REAL time: 3 mins 37 secs
Total REAL time to Placer completion: 3 mins 37 secs
Total CPU  time to Placer completion: 3 mins 31 secs
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
Mapping completed.
See MAP report file "test_map.mrp" for details.
Problem encountered during the packing phase.
Design Summary
--------------
Number of errors   :   1
Number of warnings :   1
Process "Map" failed

What can I do?

这不是同一个错误。
Pack：1654消息只是一个摘要错误消息。
在这两种情况下，如果没有打印应该继续摘要消息的主要错误消息，则设计失败。
如果比较它们在不同阶段发生的日志文件。
我建议您尝试14.1版本，这可能会提供更好的错误处理，甚至可能成功运行。
如果失败了，我建议打开一个webcase来调查。



以下为原文

This is not the same error. The Pack:1654 message is just a summary error message. In both cases the design is failing without printing the primary error message that is supposed to proceed the summary message. If you compare the log files they are occurring in different phases. I suggest that you try the 14.1 release which might provide better error handling or maybe even a successful run. If that fails I suggest opening a webcase to have this investigated.

感谢您的推荐，我在14.1版本中遇到以下错误：第1部分 - 错误------------------错误：地点：543  - 此设计不适合数字
由于设计和/或约束的复杂性，在该设备中可用的切片。
按类型放置未放置的实例：FF 3（0.2）请评估以下内容： - 如果存在用户定义的约束或区域组：请查看下面的“用户定义的约束”部分，以确定可能影响其拟合的约束条件
设计。
评估它们是否可以移动，移除或调整大小以允许拟合。
验证它们是否与时钟区域限制重叠或冲突。
有关时钟区域使用的更多详细信息，请参阅MAP日志文件（* map）中的时钟区域报告。
- 如果放置LUT有困难：尝试使用MAP LUT组合选项（映射lc区域|自动|关闭）。
- 如果放置FF有困难：评估设计中控制集的数量和配置。
以下实例是未能放置的最后一组实例：0。FF BRAM / MicroBlaze_inst / microblaze_0 / microblaze_0 / MicroBlaze_Core_I / Performance。
Use_Debug_Logic.Master_Core.Debug_Perf / Performace_Debug_Control.mem_dbg_hit_0 1. FF BRAM / MicroBlaze_inst / bram_cntlr_0 / bram_cntlr_0 / lmb_addrstrobe_i 2. FF BRAM / MicroBlaze_inst / debug_module / debug_module / MDM_Core_I1 / Config_Reg设计不大，应该适合设备。
这可能是由系统时钟引起的吗？我读过AR＃33520和AR＃35539，但这对我没有帮助。
还有别的：没有ILA-Core（ChipScope），我没有错。



以下为原文

Thanks for your recommendation,
I have the following Error with 14.1 release:

Section 1 - Errors
------------------
ERROR:Place:543 - This design does not fit into the number of slices available
   in this device due to the complexity of the design and/or constraints.
   Unplaced instances by type:
     FF    3 (0.2)
   Please evaluate the following:
   - If there are user-defined constraints or area groups:
     Please look at the "User-defined constraints" section below to determine
     what constraints might be impacting the fitting of this design.
     Evaluate if they can be moved, removed or resized to allow for fitting.
     Verify that they do not overlap or conflict with clock region restrictions.
     See the clock region reports in the MAP log file (*map) for more details
     on clock region usage.
   - If there is difficulty in placing LUTs:
     Try using the MAP LUT Combining Option (map lc area|auto|off).
   - If there is difficulty in placing FFs:
     Evaluate the number and configuration of the control sets in your design.
   The following instances are the last set of instances that failed to place:

   0. FF
   BRAM/MicroBlaze_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.
   Use_Debug_Logic.Master_Core.Debug_Perf/Performace_Debug_Control.mem_dbg_hit_0
   1. FF BRAM/MicroBlaze_inst/bram_cntlr_0/bram_cntlr_0/lmb_addrstrobe_i
   2. FF
   BRAM/MicroBlaze_inst/debug_module/debug_module/MDM_Core_I1/Config_Reg<31>

The design is not large and should fit into device. Can this be caused by system clock?
I have read AR# 33520 and AR# 35539 but that doesn’t help me.

And something else: without ILA-Core (ChipScope) I get no errors.

局部拟合问题通常是由于时钟放置限制。
对于Place：543错误中提到的F​​F，请检查所涉及的时钟域。
然后检查该时钟域的放置限制。
如果您有设计区域受限的部分，那也可能是一个因素。
请记住，错误消息中提到的物理FF组件具有从输出网络名称派生的名称，因此您要在逻辑网表中搜索网络名称以标识驱动它的FF。



以下为原文

A localized fitting problem is often due to clock placement restrictions. For the FFs mentioned in the Place:543 error, check to see what clock domain is involved. Then check the placement restrictions for that clock domain. If you have area constrained parts of the design, that could also be a factor.
 
Keep in mind that the physical FF components mentioned in the error message have names derived from the output net name so you want to search for a net name in the logical netlist to identify the FF driving it.