spartn6映射在BUFGMUX冲突时失败

gauz写道：
嗨，
在映射基于spartn6的设计时遇到错误，错误信息如下，
错误：地点：1023  - 无法安排的位置！
配置为可选择的全局时钟组件 
多路复用器放置在站点BUFGMUX_X2Y1中。
此配置要求全局时钟站点BUFGMUX_X2Y2 
空或包含全局缓冲器或多路复用器，输入IN0和IN1不是由信号驱动或由驱动器驱动 
与原始多路复用器IN1和IN0引脚分别相同的信号，以便路由两个输入。
其他 
在一个缓冲器上IN0的输入信号必须与在另一个缓冲器上驱动IN1的输入信号相同（或者 
其中一个不得被驱动）将两个缓冲区放在配对的站点中。
网站BUFGMUX_X2Y2具有全局性 
缓冲区放在那里。
此设计无法解决.ERROR：Pack：1654  - 时序驱动的放置阶段遇到错误。
有人对此有任何建议吗？
提前谢谢，高兹
仔细阅读S6 FPGA时钟资源指南UG382。
缓冲器位置和引脚选择等都有各种非显而易见的要求。
----------------------------是的，我这样做是为了谋生。



以下为原文

gauz wrote:
Hi,
It run into error when mapping my spartn6 based design,  the error info as below,
ERROR:Place:1023 - Unroutable Placement! A global clock component configured as a selectable
   mux is placed in site BUFGMUX_X2Y1.  This configuration requires that the global clock site BUFGMUX_X2Y2 either be
   empty or contain a global buffer or mux with the inputs IN0 and IN1 either not driven by a signal or driven by the
   same signals as the original muxes IN1 and IN0 pins respectively in order to route up both of the inputs.  In other
   words the input signal for IN0 on one buffer must be the same as the input signal driving IN1 on the other buffer (or
   one of them must not be driven) to place the two buffers in the paired sites.  The site BUFGMUX_X2Y2 has the global
   buffer placed there.  This design is unroutable.
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
 
Does anyone has any suggestion on this?
 
Thanks in advance,
Gauz

Carefully read the S6 FPGA Clocking Resources guide, UG382. There are all sorts of non-obvious requirements on buffer locations and pin selection and such.
----------------------------Yes, I do this for a living.

是的，但是我们的原理图和PCB已经在fpga逻辑准备好之前完成了。
除了更改位置，还有其他方法可以解决此问题吗？
非常感谢，
加斯



以下为原文

Yes, but our schematic and PCB have been done before fpga logic get ready.
Other than change location, is there any other way to fix this problem?
 
Thanks a lot,
Gauz

加斯，
您的源代码可能有问题，或者您的位置/映射约束可能存在问题。
您是否允许ISE在您的设计中放置BUFG / BUFGCE / BUFGMUX缓冲区？
我不够专业，无法清楚地理解错误信息。
另一方面，这种错误消息通常具有误导性，报告的问题是另一个错误的结果，这是问题的真正原因。
也许发布您的时钟输入/缓冲区/多路复用源代码可能会对您问题的真实性有所了解。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Gauz,
 
You may have a problem in your source code, or perhaps you may have a problem in your place/mapping constraints.  Are you allowing ISE to place the BUFG/BUFGCE/BUFGMUX buffers in your design?
 
I am not expert enough to understand the error message clearly.  On the other hand, such error messages are often misleading, reporting problems which are the consequence of another error which is the true cause of the problem.
 
Perhaps posting your clock input/buffer/mux source code might shed some light on the true nature of your problem.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

“是的，但我们的原理图和PCB已经在fpga逻辑准备就绪之前完成了。”你不会是第一个被b **咬伤的人/项目，我怀疑，也不是最后一个。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

"Yes, but our schematic and PCB have been done before fpga logic get ready."

You would not be the first person/project to be bitten in the b** by this, nor, I suspect, the last.

------------------------------------------
"If it don't work in simulation, it won't work on the board."

gauz写道：
嗨，
在映射基于spartn6的设计时遇到错误，错误信息如下，
错误：地点：1023  - 无法安排的位置！
配置为可选择的全局时钟组件 
多路复用器放置在站点BUFGMUX_X2Y1中。
此配置要求全局时钟站点BUFGMUX_X2Y2 
空或包含全局缓冲器或多路复用器，输入IN0和IN1不是由信号驱动或由驱动器驱动 
与原始多路复用器IN1和IN0引脚分别相同的信号，以便路由两个输入。
其他 
在一个缓冲器上IN0的输入信号必须与在另一个缓冲器上驱动IN1的输入信号相同（或者 
其中一个不得被驱动）将两个缓冲区放在配对的站点中。
网站BUFGMUX_X2Y2具有全局性 
缓冲区放在那里。
此设计无法解决.ERROR：Pack：1654  - 时序驱动的放置阶段遇到错误。
有人对此有任何建议吗？
提前谢谢，高兹
没有足够的信息来说明发生了什么......
但听起来你使用那些错误的引脚来完成bufgmux的时钟。
如果那些是差分时钟，你不确定你能做些什么来解决它，并且它们被锁定在错误的对上......
如果您的时钟是单端，您可能会尝试覆盖时钟网的Xilinx映射/路由规则，如下所示
NET“your_clock_ net”CLOCK_DEDICATED_ROUTE = FALSE;
祝你好运，



以下为原文

gauz wrote:
Hi,
It run into error when mapping my spartn6 based design,  the error info as below,
ERROR:Place:1023 - Unroutable Placement! A global clock component configured as a selectable
   mux is placed in site BUFGMUX_X2Y1.  This configuration requires that the global clock site BUFGMUX_X2Y2 either be
   empty or contain a global buffer or mux with the inputs IN0 and IN1 either not driven by a signal or driven by the
   same signals as the original muxes IN1 and IN0 pins respectively in order to route up both of the inputs.  In other
   words the input signal for IN0 on one buffer must be the same as the input signal driving IN1 on the other buffer (or
   one of them must not be driven) to place the two buffers in the paired sites.  The site BUFGMUX_X2Y2 has the global
   buffer placed there.  This design is unroutable.
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
 
Does anyone has any suggestion on this?
 
Thanks in advance,
Gauz

Not enough informaiton to say what's going on...
 
But it sounds like you use those wrong pins for the clocks to the ultize the bufgmux.  Not sure you can do anything to fix it if those are differential clocks, and they are locked on the wrong pair...
 
If your clocks are single end, you may try to overwrite the Xilinx mapping/routing rules for clock net, something like this
 
NET  "your_clock_ net"     CLOCK_DEDICATED_ROUTE = FALSE;
 
Good luck,
 
 

嗨，
我终于通过删除其他一些BUFGMUX单元来解决问题。
抱歉耽搁了！
谢谢你们，
纱布



以下为原文

Hi,
 
I finially fixed the problem by removing some other BUFGMUX cell.
 
Sorry for the delay!
 
Thank you all,
Gauz