放置错误：1205,1136,1654使用时钟向导生成PLL时钟

看起来问题不是时钟向导代码，而是您尝试通过obuf输出缓冲区将生成的时钟发送到输出引脚。
如果是这种情况，请在术语“时钟转发”中搜索在器件输出引脚上提供时钟信号的正确方法。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

It looks like the problem is not the clock wizard code, but that you are trying to send the generated clock to an output pin via an obuf output buffer.  If this is the case, then please search the term 'clock forwarding' for the correct method of providing a clock signal on a device output pin.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

感谢您的搜索字词！
我将尝试理解从内部时钟网络输出信号的过程。



以下为原文

Thanks for this search term! I will try to understand the procedure to output the signal from the internal clock network.

也谢谢avrumw的回答!!
它的解释比“将.D0引脚与Logic1连接;将.D1引脚连接到逻辑0;将时钟网络连接到.C0;将倒频时钟连接到.C1”。
;）
因此，ClockWizard正在生成一个实体，该实体启用内部PLL并生成内部时钟总线上可用的一个或多个时钟信号。
该总线信号既可以路由到ODDR（-entity ??），也可以路由到IO-Pin，也可以用于连接到内部时钟网络的其他内部组件。
它是否正确？
我必须找到如何在包含ODDR或其他类型逻辑的另一个实体中使用PLL信号。
向导创建以下输出缓冲区代码： 
- 输出缓冲 
------------------------------------- 
clkf_buf：BUFG 
港口地图 
（O => clkfb， 
I => clk2x）; 
clkout1_buf：BUFG 
港口地图 
（O => clk_out1_internal， 
I => clk2x）; 
CLK_OUT1
这是我可以在另一个实体中使用（以及如何）构建一个ODDR的信号吗？
第224页的ODDR代码（http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/spartan6_hdl.pdf）必须以某种方式修改我的需求。
附：
“224”是问题的路线...... XILINX在无穷无尽的页面上做得很好，描述了你可以做什么，但不知道怎么做^^。
我发现没有中等大小的教程描述多个实体或PLL的使用。
只是一些小教程 - 在这一点上易于理解和相当无用:(



以下为原文

Also thank you avrumw for your answer!!
 
Its an much better explanation than "tie the .D0 pin to Logic1; tie the .D1 pin toLogic0; tie the clock net to be forwarded to .C0; tie the inverted clock to.C1." ;)
 
So the ClockWizard is generating an entity that enables an internal PLL and generating one or several Clock signals that are available on the internal clock bus. This Bus-Signal can either be routed to an ODDR(-entity??) and than to an IO-Pin or used in other internal components that are connected to the internal clock network. Is this correct?
 
Than I have to find out how to use the PLL-Signal in another entity that incorporates an ODDR or another kind of logic. 
 
The Wizard creates the following output buffer code:
-- Output buffering  -------------------------------------  clkf_buf : BUFG  port map   (O => clkfb,    I => clk2x);  clkout1_buf : BUFG  port map   (O   => clk_out1_internal,    I   => clk2x);  CLK_OUT1 <= clk_out1_internal; 
Is this the signal I can use (and how) in another entity to build an ODDR?
 
The Code for the ODDR on page 224 (http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/spartan6_hdl.pdf) has to be modified to me needs in some way I think.
 
 
 
p.s. "224" is the route of the problem ... XILINX makes a good job on endless pages describing what you can do, but not how to do it ^^. And I found no medium sized tutorial describing the usage of more than one entity or a PLL. Just little tutorials - easy to understand and fairly useless at this point :(

我可能会理解你问题的根源......
时钟向导是一个生成组件的工具，该组件将被实例化到您的顶层设计中 - 它本身并不是顶级设计。
我现在怀疑你是否单独合成并实现了时钟向导输出。
这不是您可以做的事情的预期机制。
但是，当您要求时，尝试了这些工具。
他们意识到你的（现在）“顶级”设计有输出，并且它附加了一个OBUF（导致你看到的错误）。
因此，时钟向导创建的实体始终应该被实例化为某个其他顶级实体中的组件。
这个顶级实体是“你的FPGA”。
对于“您的FPGA”，您需要： 
- 顶级定义 
- 这包括实体声明和输入和输出定义 
- 您将有一个输入 - 输入时钟和一个输出，即生成的时钟 
- 三个实例化组件 
1）时钟向导组件的实例。
这些工具实际上通过提供.vho（我认为这是正确的后缀）来帮助您实现这一点，这是顶层设计中组件的示例实例 - 从中​​剪切线并将其粘贴到顶层，然后自定义
实例名称和端口连接。
它甚至为您提供组件声明（在VHDL中需要） 
2）ODDR的实例，如错误消息中所述连接。
C0和C1将连接到时钟向导的输出（及其反转版本）。
您可以在FPGA的用户指南中找到相关信息（在I / O章节中） 
3）OBUF的一个instand。
OBUF的I输入将连接到ODDR的Q，OBUF的O将是您的顶级输出。
同样，请参阅“用户指南”的I.O章节。
然后你应该有一个完整的顶级设计，你 
- 应该模拟 
- 可以合成，放置和路由 
- 可以下载到您的电路板（如果有的话） - 并在示波器上测量输出
祝你好运。
Avrum



以下为原文

I may understand the source of your problem...
 
The clock wizard is a tool to generate a component that is to be instantiated into your top level design - it is NOT a top level design unto itself.
 
I am now suspecting that you synthesized and implemented the clock wizard output alone. This is not an intended mechanism for what you are allowed to do.
 
However, when you asked for it, the tools tried. They realized that there were outputs of your  (now) "top level" design, and it attached an OBUF to it (which resulted int he error you saw).
 
So, the entity created by the clock wizard is always supposed to be instantiated as a component in some other top level entity. This top level entity is "your FPGA".
 
In the case of "your FPGA", you would need:
  - A top level definition
     - this includes entity declaration and input and output definitions
        - you would have one input - the input clock, and one output, the generated clock
  - Three instantiated components
    1) An instance of the clock wizard component. The tools actually help you with this by providing a .vho (I think that is the correct suffix) which is an example instantiation of the component in a top level design - cut lines from that and paste it into your top level, then customize the instance name and port connections. It even gives you the component declaration (which you need in VHDL)
    2) An instance of an ODDR, connected as described in the error message. The C0 and C1 would be connected to the output of the clock wizard (and the inverted version thereof). You can find the information for this in the User Guide for your FPGA (in the I/O chapter)
    3) An instand of an OBUF. The I input of the OBUF would be connected to the Q of the ODDR, and the O of the OBUF would be your top level output. Again, refer to the I.O chapter of the User Guide.
 
Then you should have a complete top level design, which you
   - should simulate
   - can synthesize, place, and route
   - can download to your board (if you have one) - and measure the outputs on an oscilloscope
 
Good luck.
 
Avrum

大家好
还出现了另一个问题：
我想使用DCM_SP实例而不是PLL来生成内部时钟信号。
现在，地方错误再次发生，即使 - 在使用PLL时 - 一切正常。
为了使用DCM而不是PLL生成内部时钟信号，我需要什么缓冲区（以及为什么？）？



以下为原文

Hello everyone
 
An additional question came up:
 
I want to use the DCM_SP-instance instead of the PLL to generate an internal Clock signal. Now the Place-Errors occurs again, even if - while using the PLL - everything worked fine.
 
What buffers (and why?) do I need in order to use the DCM instead of the PLL to generate an internal Clock signal?