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tify;text-indent: 40px;">我有一个时钟,它是由MMCM生成的,我可以控制它,但名义上它与内部参考时钟相差-76度。
该引脚稀疏(以下为原文 I have a CLOCK which is generated with a MMCM who's phase I can control but nominally it is -76 degrees from an internal reference clock. This pin is sparsely (< 10 flops) used internal to the FPGA but it is driven to a PIN for use with external logic. I am trying to write a constraint that I can use this clock as both my timing reference, using create_generated_clock, but more importantly I can control the delay from the MMCM to the pin. Is set_max/min_delay the right way to do this? Thanks in advance, TomT... |
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我想使用端口“p1750_hclk”作为时序约束的参考时钟,如“p1750_lackn”和“p1750_read”(这是一个输入,我粘贴了下面的时序报告)。
如何让时序分析引擎将端口“p1750_hclk”视为时钟? 这很标准...... 您需要在FPGA的输出端口创建生成的时钟 create_generated_clock -name p1750_hclk -divide_by 1 -source [get_pins hclk_ODDR_inst / C] [get_ports hclk_p1750] 如果你的ODDR进行反转(D1连接到0而D2连接到1),那么你需要-invert标志 create_generated_clock -name p1750_hclk -divide_by 1 -invert -source [get_pins hclk_ODDR_inst / C] [get_ports hclk_p1750] 这定义了端口上的时钟。 现在,这个时钟可以(并且必须)用作指定set_output_delay约束的时钟 #HCLK - > LACKN设置= 15ns(电路板延迟低于18) #HCLK - > LACKN Hold = 13ns set_output_delay -clock [get_clocks p1750_hclk] -max 18.000 [get_ports p1750_lackn] set_output_delay -clock [get_clocks p1750_hclk] -min -13.000 [get_ports p1750_lackn] 不要使用-add_delay。 -min和a -max可以同时存在于引脚上 - -add_delay仅添加第二个最大值或第二个最小值(例如,对于DDR约束)。 Avrum 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 I want to use the port "p1750_hclk" as my reference clock for the timing constraints like "p1750_lackn" and "p1750_read" (which is an input and I pasted the timing report below). How do I make the timing analysis engine consider the port "p1750_hclk" as a clock? This is pretty standard... You need to create a generated clock at the output port of the FPGA create_generated_clock -name p1750_hclk -divide_by 1 -source [get_pins hclk_ODDR_inst/C] [get_ports hclk_p1750] If your ODDR does inversion (the D1 is connected to 0 and the D2 is connected to 1), then you need the -invert flag create_generated_clock -name p1750_hclk -divide_by 1 -invert -source [get_pins hclk_ODDR_inst/C] [get_ports hclk_p1750] This defines the clock on the port. Now this clock can (and must) be used as the clock to specify the set_output_delay constraints # HCLK -> LACKN Setup = 15ns (18 below for board delay)# HCLK -> LACKN Hold = 13nsset_output_delay -clock [get_clocks p1750_hclk] -max 18.000 [get_ports p1750_lackn]set_output_delay -clock [get_clocks p1750_hclk] -min -13.000 [get_ports p1750_lackn]Don't use the -add_delay. A -min and a -max can exist on the pin at the same time - the -add_delay is only to add a second max or a second min (for example for a DDR constraint). Avrum View solution in original post |
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我不完全确定你要求的是什么......
但首先,要转发内部时钟,不要只是将它带到OBUF,而是使用ODDR。 看一下使用ODDR转发时钟的这篇文章。 接下来,您说MMCM与“内部参考”时钟相差-76度。 这一点尚不清楚 - 您的“内部参考时钟”(MMCM的输入)和MMCM时钟的输出是否有路径? 如果是这样,那么不建议这样做 - 最好将多个相关时钟作为同一MMCM的输出生成。 最后,你是什么意思“控制从MMCM到引脚的延迟”。 你不能/不应该。 从MMCM到引脚的延迟是时钟树和ODDR的延迟。 该延迟由FPGA的结构决定,并且依赖于高工艺,电压,温度(PVT)。 即使你可以“控制”它,你实施的任何控制都将在高PVT变化之上(这肯定会在几纳秒的范围内)。 那么,你真正想做什么。 有控制输出时钟的时序的机制,但这些机制要么使用ODELAY(如果引脚有ODELAY - 仅在HP IOB上可用),或者更常见的是,通过生成不同(或变化)的阶段 MMCM生成的输出时钟。 如果您告诉我们您要完成的任务,我们或许能够为您提供更多指导。 Avrum 以上来自于谷歌翻译 以下为原文 I am not entirely sure what you are asking for... But first, to forward an internal clock out, you don't just bring it to an OBUF, you use an ODDR. Take a look at this post on forwarding a clock using the ODDR. Next, you say that the MMCM is -76 degress from an "internal reference" clock. This isn't clear - do you have paths from your "internal reference clock" (the input to the MMCM) and the output of the MMCM clock? If so, then this isn't recommended - it is always better to have multiple related clocks generated as outputs of the same MMCM. Finally, what do you mean by "control the delay from the MMCM to the pin". You can't/shouldn't. The delay from the MMCM to the pin is the delay of the clock tree and and the ODDR. This delay is determined by the structure of the FPGA, and is highly process, voltage, temperature (PVT) dependent. Even if you could "control" it, any control you implement would be on top of the high PVT variation (which would certainly be in the range of several nanoseconds). So, what do you really want to do. There are mechanisms of controlling the timing of an outgoing clock, but these would either use the ODELAY (if the pin has an ODELAY - the are only available on HP IOBs), or, more normally, by generating different (or varying) phases of an output clock generated by the MMCM. If you tell us what you are trying to accomplish, we might be able to guide you further. Avrum |
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以上来自于谷歌翻译 以下为原文 Avrumw, Well after ripping out my clocking network and starting over I finally have the design P&R again. I still have a problem that I cannot seem to get the timing engine to report this path correctly. Let me draw a simple picture: MMCM +-------+ FDPE | | +-----+ | |---fclk-----o| |---lackn----[x] lackn | | +-----+ | |---fclkp--------------{ODDR}----[x] hclk +-------+ Now the signal fclk is 20MHz and fclkp is phase adjusted 20MHz. I am trying to time the arrival of lackn against hclk; please not lack is falling edge driven. The problem is I cannot seem to get the proper generated constraint for hclk? Attached is two reports, one showing the path from the MMCM to hclk and the second showing the timing report for lackn with respect to hclk. Now for hclk I created a generated clock (maybe this is the mistake) using the following command: create_generated_clock -name p1750_hclk -master_clock [get_clocks ClockReset_inst/clk_synth_inst/inst/clk_in2] -source [get_pins ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT2] -add -combinational [get_ports p1750_hclk] The goal was to have a clock named "p1750_hclk" which I could use in my timing constraints and would represent the phase and physical delay of the clock network throughout the chip. report_timing -to [get_ports p1750_hclk] INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs INFO: [Timing 38-78] ReportTimingParams: -to_pins -max_paths 1 -nworst 1 -delay_type max -sort_by slack. Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------ | Tool Version : Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015 | Date : Wed Aug 9 11:14:47 2017 | Host : athens.hdl-design.com running 64-bit CentOS release 6.9 (Final) | Command : report_timing -to [get_ports p1750_hclk] | Design : spock | Device : 7k325t-fbg900 | Speed File : -1 PRODUCTION 1.12 2014-09-11 ------------------------------------------------------------------------------------ Timing Report Slack: inf Source: hclk_ODDR_inst/C (falling edge-triggered cell ODDR clocked by clk_out3_clk_synthesizer_1 {rise@0.000ns fall@25.000ns period=50.000ns}) Destination: p1750_hclk (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 3.740ns (logic 3.740ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.501ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out3_clk_synthesizer_1 fall edge) 25.000 25.000 f BUFGCTRL_X0Y8 BUFG 0.000 25.000 f pclk_mb_to_ClockReset/O net (fo=2, routed) 2.180 27.180 ClockReset_inst/clk_synth_inst/inst/clk_in2 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT2) -5.078 22.102 f ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT2 net (fo=2, routed) 2.778 24.880 ClockReset_inst/clk_synth_inst/inst/clk_out3_clk_synthesizer BUFGCTRL_X0Y3 BUFGCTRL (Prop_bufgctrl_I0_O) 0.120 25.000 f ClockReset_inst/clk_synth_inst/inst/clkout3_buf/O net (fo=4, routed) 1.659 26.659 p1750_hclk_i OLOGIC_X0Y150 ODDR f hclk_ODDR_inst/C ------------------------------------------------------------------- ------------------- OLOGIC_X0Y150 ODDR (Prop_oddr_C_Q) 0.415 27.074 r hclk_ODDR_inst/Q net (fo=1, routed) 0.000 27.074 p1750_hclk_OBUF P19 OBUF (Prop_obuf_I_O) 3.325 30.399 r p1750_hclk_OBUF_inst/O net (fo=0) 0.000 30.399 p1750_hclk P19 r p1750_hclk (OUT) ------------------------------------------------------------------- ------------------- And for LACKN: report_timing -to [get_ports p1750_lackn] INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs INFO: [Timing 38-78] ReportTimingParams: -to_pins -max_paths 1 -nworst 1 -delay_type max -sort_by slack. Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------ | Tool Version : Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015 | Date : Wed Aug 9 11:15:15 2017 | Host : athens.hdl-design.com running 64-bit CentOS release 6.9 (Final) | Command : report_timing -to [get_ports p1750_lackn] | Design : spock | Device : 7k325t-fbg900 | Speed File : -1 PRODUCTION 1.12 2014-09-11 ------------------------------------------------------------------------------------ Timing Report Slack (VIOLATED) : -3.053ns (required time - arrival time) Source: spock_emulation_inst/Bridge_inst/lack_reg/C (falling edge-triggered cell FDPE clocked by clk_out1_clk_synthesizer_1 {rise@0.000ns fall@25.000ns period=50.000ns}) Destination: p1750_lackn (output port clocked by p1750_hclk {rise@0.000ns fall@25.000ns period=50.000ns}) Path Group: p1750_hclk Path Type: Max at Slow Process Corner Requirement: 25.000ns (p1750_hclk rise@50.000ns - clk_out1_clk_synthesizer_1 fall@25.000ns) Data Path Delay: 7.879ns (logic 3.402ns (43.179%) route 4.477ns (56.821%)) Logic Levels: 2 (LUT1=1 OBUF=1) Output Delay: 18.000ns Clock Path Skew: -1.853ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.000ns = ( 50.000 - 50.000 ) Source Clock Delay (SCD): 1.853ns = ( 26.853 - 25.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.321ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.396ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_synthesizer_1 fall edge) 25.000 25.000 f BUFGCTRL_X0Y8 BUFG 0.000 25.000 f pclk_mb_to_ClockReset/O net (fo=2, routed) 2.180 27.180 ClockReset_inst/clk_synth_inst/inst/clk_in2 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT0) -5.078 22.102 f ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT0 net (fo=2, routed) 2.778 24.880 ClockReset_inst/clk_synth_inst/inst/clk_out1_clk_synthesizer BUFGCTRL_X0Y0 BUFGCTRL (Prop_bufgctrl_I0_O) 0.120 25.000 f ClockReset_inst/clk_synth_inst/inst/clkout1_buf/O net (fo=15773, routed) 1.853 26.853 spock_emulation_inst/Bridge_inst/test_point32_OBUF SLICE_X26Y88 FDPE r spock_emulation_inst/Bridge_inst/lack_reg/C (IS_INVERTED) ------------------------------------------------------------------- ------------------- SLICE_X26Y88 FDPE (Prop_fdpe_C_Q) 0.272 27.125 f spock_emulation_inst/Bridge_inst/lack_reg/Q net (fo=20, routed) 0.162 27.287 spock_emulation_inst/Bridge_inst/lack_reg_0 SLICE_X27Y88 LUT1 (Prop_lut1_I0_O) 0.053 27.340 r spock_emulation_inst/Bridge_inst/p1750_lackn_OBUF_inst_i_1/O net (fo=1, routed) 4.315 31.655 p1750_lackn_OBUF C20 OBUF (Prop_obuf_I_O) 3.077 34.732 r p1750_lackn_OBUF_inst/O net (fo=0) 0.000 34.732 p1750_lackn C20 r p1750_lackn (OUT) ------------------------------------------------------------------- ------------------- (clock p1750_hclk rise edge) 50.000 50.000 r clock pessimism 0.000 50.000 clock uncertainty -0.321 49.679 output delay -18.000 31.679 ------------------------------------------------------------------- required time 31.679 arrival time -34.732 ------------------------------------------------------------------- slack -3.053 How can I get a clock at the pin which I can use for my constraints? Thanks, TomT... |
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以上来自于谷歌翻译 以下为原文 More info, hope it isn't overwhelming. If I define the p1750_hclk as: create_generated_clock -name p1750_hclk -master_clock [get_clocks ClockReset_inst/clk_synth_inst/inst/clk_in2] -source [get_pins ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT2] -add -divide_by 1 [get_ports p1750_hclk] I get the following timing for LACKN (which shows the proper hclk delay, but is missing the edge of the phase delay)? report_timing -to [get_ports p1750_lackn] INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs INFO: [Timing 38-78] ReportTimingParams: -to_pins -max_paths 1 -nworst 1 -delay_type max -sort_by slack. Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------ | Tool Version : Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015 | Date : Wed Aug 9 14:39:33 2017 | Host : athens.hdl-design.com running 64-bit CentOS release 6.9 (Final) | Command : report_timing -to [get_ports p1750_lackn] | Design : spock | Device : 7k325t-fbg900 | Speed File : -1 PRODUCTION 1.12 2014-09-11 ------------------------------------------------------------------------------------ Timing Report Slack (MET) : 0.869ns (required time - arrival time) Source: spock_emulation_inst/Bridge_inst/lack_reg/C (falling edge-triggered cell FDPE clocked by clk_out1_clk_synthesizer_1 {rise@0.000ns fall@25.000ns period=50.000ns}) Destination: p1750_lackn (output port clocked by p1750_hclk {rise@0.000ns fall@25.000ns period=50.000ns}) Path Group: p1750_hclk Path Type: Max at Slow Process Corner Requirement: 25.000ns (p1750_hclk rise@50.000ns - clk_out1_clk_synthesizer_1 fall@25.000ns) Data Path Delay: 8.685ns (logic 3.445ns (39.668%) route 5.240ns (60.332%)) Logic Levels: 2 (LUT1=1 OBUF=1) Output Delay: 18.000ns Clock Path Skew: 2.876ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.867ns = ( 54.867 - 50.000 ) Source Clock Delay (SCD): 1.856ns = ( 26.856 - 25.000 ) Clock Pessimism Removal (CPR): -0.135ns Clock Uncertainty: 0.321ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.396ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_synthesizer_1 fall edge) 25.000 25.000 f BUFGCTRL_X0Y8 BUFG 0.000 25.000 f pclk_mb_to_ClockReset/O net (fo=2, routed) 2.180 27.180 ClockReset_inst/clk_synth_inst/inst/clk_in2 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT0) -5.078 22.102 f ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT0 net (fo=2, routed) 2.778 24.880 ClockReset_inst/clk_synth_inst/inst/clk_out1_clk_synthesizer BUFGCTRL_X0Y0 BUFGCTRL (Prop_bufgctrl_I0_O) 0.120 25.000 f ClockReset_inst/clk_synth_inst/inst/clkout1_buf/O net (fo=15773, routed) 1.856 26.856 spock_emulation_inst/Bridge_inst/test_point32_OBUF SLICE_X8Y84 FDPE r spock_emulation_inst/Bridge_inst/lack_reg/C (IS_INVERTED) ------------------------------------------------------------------- ------------------- SLICE_X8Y84 FDPE (Prop_fdpe_C_Q) 0.315 27.171 f spock_emulation_inst/Bridge_inst/lack_reg/Q net (fo=20, routed) 0.923 28.094 spock_emulation_inst/Bridge_inst/lack_reg_0 SLICE_X30Y86 LUT1 (Prop_lut1_I0_O) 0.053 28.147 r spock_emulation_inst/Bridge_inst/p1750_lackn_OBUF_inst_i_1/O net (fo=1, routed) 4.317 32.464 p1750_lackn_OBUF C20 OBUF (Prop_obuf_I_O) 3.077 35.541 r p1750_lackn_OBUF_inst/O net (fo=0) 0.000 35.541 p1750_lackn C20 r p1750_lackn (OUT) ------------------------------------------------------------------- ------------------- (clock p1750_hclk rise edge) 50.000 50.000 f BUFGCTRL_X0Y8 BUFG 0.000 50.000 f pclk_mb_to_ClockReset/O net (fo=2, routed) 2.046 52.046 ClockReset_inst/clk_synth_inst/inst/clk_in2 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT2) -4.809 47.237 f ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT2 net (fo=2, routed) 2.650 49.887 ClockReset_inst/clk_synth_inst/inst/clk_out3_clk_synthesizer BUFGCTRL_X0Y3 BUFGCTRL (Prop_bufgctrl_I0_O) 0.113 50.000 f ClockReset_inst/clk_synth_inst/inst/clkout3_buf/O net (fo=4, routed) 1.493 51.493 p1750_hclk_i OLOGIC_X0Y150 ODDR (Prop_oddr_C_Q) 0.360 51.853 r hclk_ODDR_inst/Q net (fo=1, routed) 0.000 51.853 p1750_hclk_OBUF P19 OBUF (Prop_obuf_I_O) 3.014 54.867 r p1750_hclk_OBUF_inst/O net (fo=0) 0.000 54.867 p1750_hclk P19 r p1750_hclk (OUT) clock pessimism -0.135 54.732 clock uncertainty -0.321 54.410 output delay -18.000 36.410 ------------------------------------------------------------------- required time 36.410 arrival time -35.541 ------------------------------------------------------------------- slack 0.869 I will try another iteration to see if I can get the p1750_hclk to show the edge change of the phase delay? Thanks, TomT... |
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好的 - 先......
create_generated_clock -name p1750_hclk -master_clock [get_clocks ClockReset_inst / clk_synth_inst / inst / clk_in2] -source [get_pins ClockReset_inst / clk_synth_inst / inst / mmcm_adv_inst / CLKOUT2] -add -combinational [get_ports p1750_hclk] 这是错的。 -combinational标志不会按照您的想法执行。 你需要使用-divide_by 1或-multiply_by 1,你不能使用-combinational(它意味着别的东西)。 您也不应该使用-add标志。 它可能是无害的,但不要这样做。 您也不需要-master_clock选项 - 只有在-source携带多个时钟时才需要这个(这是一种非常罕见的情况)。 作为一种形式,传统上使用-source作为ODDR的输入C引脚,而不是MMCM的输出。 我认为它们最终是同一个东西,但是如果使用ODDR的C引脚则更清楚。 不幸的是,由于换行,您的计时报告很难阅读 - 请将它们发布在“插入代码”框中,以便保留格式(和非比例字体)。 接下来,看起来您的主时钟从MMCM的输出开始。 情况并非如此。 你永远不应该(很少,很少)在FPGA的内部节点上做一个“create_clock”。 对于这种设计,您应该在端口上有一个create_clock命令,它将外部时钟带入FPGA。 然后,这些工具将自动生成具有适当关系的MMCM出来的时钟。 您还需要向我们展示您想要约束的输出的时序约束 - 如果它们没有正确完成(使用生成的时钟),那么报告将毫无意义。 告诉我们你所有的时间限制...... Avrum 以上来自于谷歌翻译 以下为原文 OK - first... create_generated_clock -name p1750_hclk -master_clock [get_clocks ClockReset_inst/clk_synth_inst/inst/clk_in2] -source [get_pins ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT2] -add -combinational [get_ports p1750_hclk] This is wrong. The -combinational flag does not do what you think it does. You need to use -divide_by 1 or -multiply_by 1, you cannot use -combinational (it means something else). You should also not use the -add flag. It is probably harmless, but don't do it. You also don't need the -master_clock option - this is only needed if the -source is carrying multiple clocks (which is a very rare case). As a point of form, it is traditional to use the -source as being the input C pin to the ODDR, rather than the output of the MMCM. I think they end up being the same thing, but it is clearer if you use the C pin of the ODDR. Unfortunately your timing reports are very hard to read due to line wrapping - please post them in an "Insert Code" box so that the formatting (and non-proportional fonts) are preserved. Next, it looks like your primary clock starts at the output of the MMCM. This should not be the case. You should never (well, rarely) do a "create_clock" on an internal node of the FPGA. For this design, you should have a single create_clock command on the port which brings the external clock into your FPGA. The tools will then automatically generate the clocks coming out of the MMCM with the proper relationships. You also need to show us your timing constraints for the outputs you want to constrain - if they aren't done correctly (using the generated clock) then the reports will be meaningless. Show us all your timing constraints... Avrum |
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以上来自于谷歌翻译 以下为原文 Avrumw, Thanks for the feedback. Going back to the picture above, I need a -source to ensure that we are picking up the correct input as I have a set_case_analysis to only time through the primary (production) clock source. I was actually trying to rename the ODDR output pin to be a Clock which I can use for reference to my external device. The ODDR is driving a clock to other OFF CHIP logic. The problem I am having is getting this clock to properly account for the "phase delay" that I have put into place at the MMCM. As you can tell if I use -divide_by 1 then I am creating a new clock and that clock assumes the edges are at 0, 25 and 50. Instead of what they are due to the phase changes which is -10, 15 40 for example. So below is an example timing path for the signal lackn (I know it says it passes which is good) but the analysis is flawed because the p1750_hclk clock is not using the correct edges. report_timing -to [get_port p1750_lackn]INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: max.INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUsINFO: [Timing 38-78] ReportTimingParams: -to_pins -max_paths 1 -nworst 1 -delay_type max -sort_by slack.Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.------------------------------------------------------------------------------------| Tool Version : Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015| Date : Thu Aug 17 12:28:27 2017| Host : athens.hdl-design.com running 64-bit CentOS release 6.9 (Final)| Command : report_timing -to [get_ports p1750_lackn]| Design : spock| Device : 7k325t-fbg900| Speed File : -1 PRODUCTION 1.12 2014-09-11------------------------------------------------------------------------------------Timing ReportSlack (MET) : 1.307ns (required time - arrival time) Source: spock_emulation_inst/Bridge_inst/lack_reg/C (falling edge-triggered cell FDPE clocked by clk_out1_clk_synthesizer_1 {rise@0.000ns fall@25.000ns period=50.000ns}) Destination: p1750_lackn (output port clocked by p1750_hclk {rise@0.000ns fall@25.000ns period=50.000ns}) Path Group: p1750_hclk Path Type: Max at Slow Process Corner Requirement: 25.000ns (p1750_hclk rise@50.000ns - clk_out1_clk_synthesizer_1 fall@25.000ns) Data Path Delay: 8.640ns (logic 3.402ns (39.377%) route 5.238ns (60.623%)) Logic Levels: 2 (LUT1=1 OBUF=1) Output Delay: 18.000ns Clock Path Skew: 3.349ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.867ns = ( 54.867 - 50.000 ) Source Clock Delay (SCD): 1.383ns = ( 26.383 - 25.000 ) Clock Pessimism Removal (CPR): -0.135ns Clock Uncertainty: 0.402ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.559ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_synthesizer_1 fall edge) 25.000 25.000 f BUFGCTRL_X0Y8 BUFG 0.000 25.000 f pclk_mb_to_ClockReset/O net (fo=2, routed) 2.180 27.180 ClockReset_inst/clk_synth_inst/inst/clk_in2 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT0) -5.078 22.102 f ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT0 net (fo=2, routed) 2.778 24.880 ClockReset_inst/clk_synth_inst/inst/clk_out1_clk_synthesizer BUFGCTRL_X0Y0 BUFGCTRL (Prop_bufgctrl_I0_O) 0.120 25.000 f ClockReset_inst/clk_synth_inst/inst/clkout1_buf/O net (fo=15938, routed) 1.383 26.383 spock_emulation_inst/Bridge_inst/test_point32_OBUF SLICE_X80Y178 FDPE r spock_emulation_inst/Bridge_inst/lack_reg/C (IS_INVERTED) ------------------------------------------------------------------- ------------------- SLICE_X80Y178 FDPE (Prop_fdpe_C_Q) 0.272 26.655 f spock_emulation_inst/Bridge_inst/lack_reg/Q net (fo=23, routed) 1.433 28.088 spock_emulation_inst/Bridge_inst/lack_reg_0 SLICE_X53Y204 LUT1 (Prop_lut1_I0_O) 0.053 28.141 r spock_emulation_inst/Bridge_inst/p1750_lackn_OBUF_inst_i_1/O net (fo=3, routed) 3.805 31.946 p1750_lackn_OBUF C20 OBUF (Prop_obuf_I_O) 3.077 35.023 r p1750_lackn_OBUF_inst/O net (fo=0) 0.000 35.023 p1750_lackn C20 r p1750_lackn (OUT) ------------------------------------------------------------------- ------------------- (clock p1750_hclk rise edge) 50.000 50.000 f BUFGCTRL_X0Y8 BUFG 0.000 50.000 f pclk_mb_to_ClockReset/O net (fo=2, routed) 2.046 52.046 ClockReset_inst/clk_synth_inst/inst/clk_in2 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT2) -4.809 47.237 f ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT2 net (fo=2, routed) 2.650 49.887 ClockReset_inst/clk_synth_inst/inst/clk_out3_clk_synthesizer BUFGCTRL_X0Y3 BUFGCTRL (Prop_bufgctrl_I0_O) 0.113 50.000 f ClockReset_inst/clk_synth_inst/inst/clkout3_buf/O net (fo=6, routed) 1.493 51.493 p1750_hclk_i OLOGIC_X0Y150 ODDR (Prop_oddr_C_Q) 0.360 51.853 r hclk_ODDR_inst/Q net (fo=1, routed) 0.000 51.853 p1750_hclk_OBUF P19 OBUF (Prop_obuf_I_O) 3.014 54.867 r p1750_hclk_OBUF_inst/O net (fo=0) 0.000 54.867 p1750_hclk P19 r p1750_hclk (OUT) clock pessimism -0.135 54.732 clock uncertainty -0.402 54.330 output delay -18.000 36.330 ------------------------------------------------------------------- required time 36.330 arrival time -35.023 ------------------------------------------------------------------- slack 1.307 Within the MMCM: ClockReset_inst/clk_synth_inst/inst/clkout3 I have the following attribute (taken from the XCI file): Which basically says that clkout3 should have a phase delay of -50 degrees ~7ns. Since clkout3 is the source of the p1750_hclk CLOCK I would expect the edges to be modified, but instead it shows up at 50ns (was expecting 43ns). Now in this case the timing for this signal gets better but for inputs with respect to this clock it gets worst. I am trying to find the sweet spot. Now for timing constraints I will past them in below for this signal of interest: # Using the GVSC Data Sheet we have the following values:# Using the values for LACKN# HCLK -> LACKN Setup = 15ns (18 below for board delay)# HCLK -> LACKN Hold = 13nsset_output_delay -max -clock [get_clocks p1750_hclk] 18 [get_ports p1750_lackn]set_output_delay -min -clock [get_clocks p1750_hclk] -13 -add_delay [get_ports p1750_lackn]Yes that is 13 ns of Hold time which is why you see this functionally being launched from the falling_edge. So for the p1750_hclk I did the following (note I also put in my rename which didn't work as I expected) # tdt 170809 rename: create_generated_clock -name p1750_hclk -master_clock [get_clocks ClockReset_inst/clk_synth_inst/inst/clk_in2] [get_pins ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT2]# Create Generated Clock at the FPGA Pin for analysis:create_generated_clock -name p1750_hclk -master_clock [get_clocks ClockReset_inst/clk_synth_inst/inst/clk_in2] -source [get_pins ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT2] -add -divide_by 1 [get_ports p1750_hclk]So I know what I am looking at in the timing reports is wrong. I just haven't found the secret to making it correct! Thanks in advance for the assistance. TomT... |
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所以你还没有解决我之前提到的几个问题:
- 你在FPGA内部创建了一个主时钟 - 源时钟延迟从BUFG开始,而不是从时钟引脚开始 - 你正在重写MMCM自动生成的时钟 - 你不应该这样做 无论您认为与时钟边缘有什么问题,都必须正确解决,而不是试图覆盖自动生成的时钟。 你还没有给我 - 时序路径的完整原理图 - 从时钟引脚引脚到ODDR(p1750_hclk)和数据输出(p1750_lack) - 完整的约束集 由于clkout3是p1750_hclk CLOCK的源 不,不是。 从此处显示的时序路径,CLKOUT2是产生p1750_hclk的源时钟,而您正在将相移应用于CLKOUT3。 这一直是问题吗? Avrum 以上来自于谷歌翻译 以下为原文 So you still haven't addressed several of the issues I mentioned before: - you have a primary clock created inside the FPGA - source clock delay starts at a BUFG, not at a clock pin - you are overriding the automatically generated clocks of the MMCM - you should not do that Whatever problem you think you are having with the edges of the clock must be solved properly, not by trying to override the automatically generated clocks. You still haven't given me either - the complete schematic of the timing path - from the clock pin pin to the ODDR (p1750_hclk) and the data output (p1750_lack) - the complete set of constraints Since clkout3 is the source of the p1750_hclk CLOCK No it isn't. From the timing path you show here, CLKOUT2 is the source clock generating p1750_hclk, whereas you are applying the phase shift to CLKOUT3. Has this been the problem all along? Avrum |
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以上来自于谷歌翻译 以下为原文 Avrumw, 1) I cannot determine why the source clock starts at a BUFG other than I have hand instantiated a BUFG from this clock pin in order to split it at the clock pin source; that is there is TWO BUFG's attached to this pin which makes this an interesting design. For the moment can we put this aside. In all of my constraints I only have the following create_clocks commands (there are NO MORE generated clocks created by me): ClocksAndReset.xdc:create_clock -period 50.000 -name mb_clk [get_ports pclk_in_mb]ClocksAndReset.xdc:create_clock -period 50.000 -name osc_clk [get_ports pclk_osc]pcieConstraints.xdc:create_clock -period 10.000 -name ext_pcie_refclk -waveform {0.000 5.000} [get_ports EXT_PCIE_REFCLK_P]2) I have removed all overriding of the MMCM by using the following method you recommended (I now use the TCL variables directly for all clock references): set fclk4x [get_clocks -of_objects [get_pins ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT1]]set fclk [get_clocks -of_objects [get_pins ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT0]]set hclk [get_clocks -of_objects [get_pins ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT2]]set sclk [get_clocks -of_objects [get_pins ClockReset_inst/clk_other_inst/inst/mmcm_adv_inst/CLKOUT1]]# renamecreate_generated_clock -name clk16m -master_clock ClockReset_inst/clk_other_inst/inst/clk_in2 [get_pins ClockReset_inst/clk_other_inst/inst/mmcm_adv_inst/CLKOUT1]3) Here is the timing report for the output port p1750_hclk: report_timing -to [get_port p1750_hclk]INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: max.INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUsINFO: [Timing 38-78] ReportTimingParams: -to_pins -max_paths 1 -nworst 1 -delay_type max -sort_by slack.Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.------------------------------------------------------------------------------------| Tool Version : Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015| Date : Mon Aug 21 16:21:54 2017| Host : athens.hdl-design.com running 64-bit CentOS release 6.9 (Final)| Command : report_timing -to [get_ports p1750_hclk]| Design : spock| Device : 7k325t-fbg900| Speed File : -1 PRODUCTION 1.12 2014-09-11------------------------------------------------------------------------------------Timing ReportSlack: inf Source: hclk_ODDR_inst/C (falling edge-triggered cell ODDR clocked by clk_out3_clk_synthesizer_1 {rise@0.000ns fall@25.000ns period=50.000ns}) Destination: p1750_hclk (output port) Path Group: (none) Path Type: Max at Slow Process Corner Data Path Delay: 3.740ns (logic 3.740ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.501ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out3_clk_synthesizer_1 fall edge) 25.000 25.000 f BUFGCTRL_X0Y8 BUFG 0.000 25.000 f pclk_mb_to_ClockReset/O net (fo=2, routed) 2.180 27.180 ClockReset_inst/clk_synth_inst/inst/clk_in2 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT2) -5.078 22.102 f ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT2 net (fo=2, routed) 2.778 24.880 ClockReset_inst/clk_synth_inst/inst/clk_out3_clk_synthesizer BUFGCTRL_X0Y3 BUFGCTRL (Prop_bufgctrl_I0_O) 0.120 25.000 f ClockReset_inst/clk_synth_inst/inst/clkout3_buf/O net (fo=6, routed) 1.659 26.659 p1750_hclk_i OLOGIC_X0Y150 ODDR f hclk_ODDR_inst/C ------------------------------------------------------------------- ------------------- OLOGIC_X0Y150 ODDR (Prop_oddr_C_Q) 0.415 27.074 r hclk_ODDR_inst/Q net (fo=1, routed) 0.000 27.074 p1750_hclk_OBUF P19 OBUF (Prop_obuf_I_O) 3.325 30.399 r p1750_hclk_OBUF_inst/O net (fo=0) 0.000 30.399 p1750_hclk P19 r p1750_hclk (OUT) ------------------------------------------------------------------- -------------------4) Here is the timing report for the path to lackn (there are 4 paths reported): report_timing -to [get_port p1750_lackn] -nworst 5INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: max.INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUsINFO: [Timing 38-78] ReportTimingParams: -to_pins -max_paths 1 -nworst 5 -delay_type max -sort_by slack.Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.------------------------------------------------------------------------------------| Tool Version : Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015| Date : Mon Aug 21 16:23:26 2017| Host : athens.hdl-design.com running 64-bit CentOS release 6.9 (Final)| Command : report_timing -to [get_ports p1750_lackn] -nworst 5| Design : spock| Device : 7k325t-fbg900| Speed File : -1 PRODUCTION 1.12 2014-09-11------------------------------------------------------------------------------------Timing ReportSlack (VIOLATED) : -3.134ns (required time - arrival time) Source: spock_emulation_inst/Bridge_inst/lack_reg/C (falling edge-triggered cell FDPE clocked by clk_out1_clk_synthesizer_1 {rise@0.000ns fall@25.000ns period=50.000ns}) Destination: p1750_lackn (output port clocked by clk_out3_clk_synthesizer_1 {rise@0.000ns fall@25.000ns period=50.000ns}) Path Group: clk_out3_clk_synthesizer_1 Path Type: Max at Slow Process Corner Requirement: 25.000ns (clk_out3_clk_synthesizer_1 rise@50.000ns - clk_out1_clk_synthesizer_1 fall@25.000ns) Data Path Delay: 5.389ns (logic 3.402ns (63.137%) route 1.986ns (36.863%)) Logic Levels: 2 (LUT1=1 OBUF=1) Output Delay: 18.000ns Clock Path Skew: -4.424ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.763ns = ( 47.237 - 50.000 ) Source Clock Delay (SCD): 1.526ns = ( 26.526 - 25.000 ) Clock Pessimism Removal (CPR): -0.135ns Clock Uncertainty: 0.321ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.396ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_synthesizer_1 fall edge) 25.000 25.000 f BUFGCTRL_X0Y8 BUFG 0.000 25.000 f pclk_mb_to_ClockReset/O net (fo=2, routed) 2.180 27.180 ClockReset_inst/clk_synth_inst/inst/clk_in2 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT0) -5.078 22.102 f ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT0 net (fo=2, routed) 2.778 24.880 ClockReset_inst/clk_synth_inst/inst/clk_out1_clk_synthesizer BUFGCTRL_X0Y0 BUFGCTRL (Prop_bufgctrl_I0_O) 0.120 25.000 f ClockReset_inst/clk_synth_inst/inst/clkout1_buf/O net (fo=15937, routed) 1.526 26.526 spock_emulation_inst/Bridge_inst/test_point32_OBUF SLICE_X1Y242 FDPE r spock_emulation_inst/Bridge_inst/lack_reg/C (IS_INVERTED) ------------------------------------------------------------------- ------------------- SLICE_X1Y242 FDPE (Prop_fdpe_C_Q) 0.272 26.798 f spock_emulation_inst/Bridge_inst/lack_reg/Q net (fo=24, routed) 0.249 27.047 spock_emulation_inst/Bridge_inst/lack_reg_0 SLICE_X3Y242 LUT1 (Prop_lut1_I0_O) 0.053 27.100 r spock_emulation_inst/Bridge_inst/p1750_lackn_OBUF_inst_i_1/O net (fo=3, routed) 1.737 28.837 p1750_lackn_OBUF C20 OBUF (Prop_obuf_I_O) 3.077 31.915 r p1750_lackn_OBUF_inst/O net (fo=0) 0.000 31.915 p1750_lackn C20 r p1750_lackn (OUT) ------------------------------------------------------------------- ------------------- (clock clk_out3_clk_synthesizer_1 rise edge) 50.000 50.000 r BUFGCTRL_X0Y8 BUFG 0.000 50.000 r pclk_mb_to_ClockReset/O net (fo=2, routed) 2.046 52.046 ClockReset_inst/clk_synth_inst/inst/clk_in2 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT2) -4.809 47.237 r ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT2 clock pessimism -0.135 47.102 clock uncertainty -0.321 46.781 output delay -18.000 28.781 ------------------------------------------------------------------- required time 28.781 arrival time -31.915 ------------------------------------------------------------------- slack -3.134 Slack (VIOLATED) : -3.134ns (required time - arrival time) Source: spock_emulation_inst/Bridge_inst/lack_reg/C (falling edge-triggered cell FDPE clocked by clk_out1_clk_synthesizer_1 {rise@0.000ns fall@25.000ns period=50.000ns}) Destination: p1750_lackn (output port clocked by clk_out3_clk_synthesizer_1 {rise@0.000ns fall@25.000ns period=50.000ns}) Path Group: clk_out3_clk_synthesizer_1 Path Type: Max at Slow Process Corner Requirement: 25.000ns (clk_out3_clk_synthesizer_1 rise@50.000ns - clk_out1_clk_synthesizer_1 fall@25.000ns) Data Path Delay: 5.389ns (logic 3.402ns (63.137%) route 1.986ns (36.863%)) Logic Levels: 2 (LUT1=1 OBUF=1) Output Delay: 18.000ns Clock Path Skew: -4.424ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -2.763ns = ( 47.237 - 50.000 ) Source Clock Delay (SCD): 1.526ns = ( 26.526 - 25.000 ) Clock Pessimism Removal (CPR): -0.135ns Clock Uncertainty: 0.321ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.396ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_synthesizer_1 fall edge) 25.000 25.000 f BUFGCTRL_X0Y8 BUFG 0.000 25.000 f pclk_mb_to_ClockReset/O net (fo=2, routed) 2.180 27.180 ClockReset_inst/clk_synth_inst/inst/clk_in2 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT0) -5.078 22.102 f ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT0 net (fo=2, routed) 2.778 24.880 ClockReset_inst/clk_synth_inst/inst/clk_out1_clk_synthesizer BUFGCTRL_X0Y0 BUFGCTRL (Prop_bufgctrl_I0_O) 0.120 25.000 f ClockReset_inst/clk_synth_inst/inst/clkout1_buf/O net (fo=15937, routed) 1.526 26.526 spock_emulation_inst/Bridge_inst/test_point32_OBUF SLICE_X1Y242 FDPE r spock_emulation_inst/Bridge_inst/lack_reg/C (IS_INVERTED) ------------------------------------------------------------------- ------------------- SLICE_X1Y242 FDPE (Prop_fdpe_C_Q) 0.272 26.798 r spock_emulation_inst/Bridge_inst/lack_reg/Q net (fo=24, routed) 0.249 27.047 spock_emulation_inst/Bridge_inst/lack_reg_0 SLICE_X3Y242 LUT1 (Prop_lut1_I0_O) 0.053 27.100 f spock_emulation_inst/Bridge_inst/p1750_lackn_OBUF_inst_i_1/O net (fo=3, routed) 1.737 28.837 p1750_lackn_OBUF C20 OBUF (Prop_obuf_I_O) 3.077 31.915 f p1750_lackn_OBUF_inst/O net (fo=0) 0.000 31.915 p1750_lackn C20 f p1750_lackn (OUT) ------------------------------------------------------------------- ------------------- (clock clk_out3_clk_synthesizer_1 rise edge) 50.000 50.000 r BUFGCTRL_X0Y8 BUFG 0.000 50.000 r pclk_mb_to_ClockReset/O net (fo=2, routed) 2.046 52.046 ClockReset_inst/clk_synth_inst/inst/clk_in2 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT2) -4.809 47.237 r ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT2 clock pessimism -0.135 47.102 clock uncertainty -0.321 46.781 output delay -18.000 28.781 ------------------------------------------------------------------- required time 28.781 arrival time -31.915 ------------------------------------------------------------------- slack -3.134 Slack (MET) : 1.711ns (required time - arrival time) Source: spock_emulation_inst/Bridge_inst/lack_reg/C (falling edge-triggered cell FDPE clocked by clk_out1_clk_synthesizer_1 {rise@0.000ns fall@25.000ns period=50.000ns}) Destination: p1750_lackn (output port clocked by clk_out3_clk_synthesizer_1 {rise@0.000ns fall@25.000ns period=50.000ns}) Path Group: clk_out3_clk_synthesizer_1 Path Type: Max at Fast Process Corner Requirement: 25.000ns (clk_out3_clk_synthesizer_1 rise@50.000ns - clk_out1_clk_synthesizer_1 fall@25.000ns) Data Path Delay: 2.920ns (logic 2.034ns (69.674%) route 0.885ns (30.326%)) Logic Levels: 2 (LUT1=1 OBUF=1) Output Delay: 18.000ns Clock Path Skew: -2.048ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.161ns = ( 48.839 - 50.000 ) Source Clock Delay (SCD): 0.814ns = ( 25.814 - 25.000 ) Clock Pessimism Removal (CPR): -0.073ns Clock Uncertainty: 0.321ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.396ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_synthesizer_1 fall edge) 25.000 25.000 f BUFGCTRL_X0Y8 BUFG 0.000 25.000 f pclk_mb_to_ClockReset/O net (fo=2, routed) 1.030 26.030 ClockReset_inst/clk_synth_inst/inst/clk_in2 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT0) -2.264 23.766 f ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT0 net (fo=2, routed) 1.204 24.970 ClockReset_inst/clk_synth_inst/inst/clk_out1_clk_synthesizer BUFGCTRL_X0Y0 BUFGCTRL (Prop_bufgctrl_I0_O) 0.030 25.000 f ClockReset_inst/clk_synth_inst/inst/clkout1_buf/O net (fo=15937, routed) 0.814 25.814 spock_emulation_inst/Bridge_inst/test_point32_OBUF SLICE_X1Y242 FDPE r spock_emulation_inst/Bridge_inst/lack_reg/C (IS_INVERTED) ------------------------------------------------------------------- ------------------- SLICE_X1Y242 FDPE (Prop_fdpe_C_Q) 0.132 25.946 f spock_emulation_inst/Bridge_inst/lack_reg/Q net (fo=24, routed) 0.133 26.079 spock_emulation_inst/Bridge_inst/lack_reg_0 SLICE_X3Y242 LUT1 (Prop_lut1_I0_O) 0.035 26.114 r spock_emulation_inst/Bridge_inst/p1750_lackn_OBUF_inst_i_1/O net (fo=3, routed) 0.752 26.866 p1750_lackn_OBUF C20 OBUF (Prop_obuf_I_O) 1.867 28.734 r p1750_lackn_OBUF_inst/O net (fo=0) 0.000 28.734 p1750_lackn C20 r p1750_lackn (OUT) ------------------------------------------------------------------- ------------------- (clock clk_out3_clk_synthesizer_1 rise edge) 50.000 50.000 r BUFGCTRL_X0Y8 BUFG 0.000 50.000 r pclk_mb_to_ClockReset/O net (fo=2, routed) 0.761 50.761 ClockReset_inst/clk_synth_inst/inst/clk_in2 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT2) -1.922 48.839 r ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT2 clock pessimism -0.073 48.766 clock uncertainty -0.321 48.445 output delay -18.000 30.445 ------------------------------------------------------------------- required time 30.445 arrival time -28.734 ------------------------------------------------------------------- slack 1.711 Slack (MET) : 1.711ns (required time - arrival time) Source: spock_emulation_inst/Bridge_inst/lack_reg/C (falling edge-triggered cell FDPE clocked by clk_out1_clk_synthesizer_1 {rise@0.000ns fall@25.000ns period=50.000ns}) Destination: p1750_lackn (output port clocked by clk_out3_clk_synthesizer_1 {rise@0.000ns fall@25.000ns period=50.000ns}) Path Group: clk_out3_clk_synthesizer_1 Path Type: Max at Fast Process Corner Requirement: 25.000ns (clk_out3_clk_synthesizer_1 rise@50.000ns - clk_out1_clk_synthesizer_1 fall@25.000ns) Data Path Delay: 2.920ns (logic 2.034ns (69.674%) route 0.885ns (30.326%)) Logic Levels: 2 (LUT1=1 OBUF=1) Output Delay: 18.000ns Clock Path Skew: -2.048ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.161ns = ( 48.839 - 50.000 ) Source Clock Delay (SCD): 0.814ns = ( 25.814 - 25.000 ) Clock Pessimism Removal (CPR): -0.073ns Clock Uncertainty: 0.321ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.396ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_synthesizer_1 fall edge) 25.000 25.000 f BUFGCTRL_X0Y8 BUFG 0.000 25.000 f pclk_mb_to_ClockReset/O net (fo=2, routed) 1.030 26.030 ClockReset_inst/clk_synth_inst/inst/clk_in2 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT0) -2.264 23.766 f ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT0 net (fo=2, routed) 1.204 24.970 ClockReset_inst/clk_synth_inst/inst/clk_out1_clk_synthesizer BUFGCTRL_X0Y0 BUFGCTRL (Prop_bufgctrl_I0_O) 0.030 25.000 f ClockReset_inst/clk_synth_inst/inst/clkout1_buf/O net (fo=15937, routed) 0.814 25.814 spock_emulation_inst/Bridge_inst/test_point32_OBUF SLICE_X1Y242 FDPE r spock_emulation_inst/Bridge_inst/lack_reg/C (IS_INVERTED) ------------------------------------------------------------------- ------------------- SLICE_X1Y242 FDPE (Prop_fdpe_C_Q) 0.132 25.946 r spock_emulation_inst/Bridge_inst/lack_reg/Q net (fo=24, routed) 0.133 26.079 spock_emulation_inst/Bridge_inst/lack_reg_0 SLICE_X3Y242 LUT1 (Prop_lut1_I0_O) 0.035 26.114 f spock_emulation_inst/Bridge_inst/p1750_lackn_OBUF_inst_i_1/O net (fo=3, routed) 0.752 26.866 p1750_lackn_OBUF C20 OBUF (Prop_obuf_I_O) 1.867 28.734 f p1750_lackn_OBUF_inst/O net (fo=0) 0.000 28.734 p1750_lackn C20 f p1750_lackn (OUT) ------------------------------------------------------------------- ------------------- (clock clk_out3_clk_synthesizer_1 rise edge) 50.000 50.000 r BUFGCTRL_X0Y8 BUFG 0.000 50.000 r pclk_mb_to_ClockReset/O net (fo=2, routed) 0.761 50.761 ClockReset_inst/clk_synth_inst/inst/clk_in2 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT2) -1.922 48.839 r ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT2 clock pessimism -0.073 48.766 clock uncertainty -0.321 48.445 output delay -18.000 30.445 ------------------------------------------------------------------- required time 30.445 arrival time -28.734 ------------------------------------------------------------------- slack 1.711 5) Here are the constraints for LACKN and the variables Assigned so you can track them: set hclk [get_clocks -of_objects [get_pins ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT2]]# HCLK -> LACKN Setup = 15ns (18 below for board delay)# HCLK -> LACKN Hold = 13nsset_output_delay -clock $hclk -max 18.000 [get_ports p1750_lackn]set_output_delay -clock $hclk -min -add_delay -13.000 [get_ports p1750_lackn]Finally, I am sorry for the mistakes in my previous post, I was reworking the clocking and got confused as to which clock I was talking about. Questions for you: 1) I want to use the port "p1750_hclk" as my reference clock for the timing constraints like "p1750_lackn" and "p1750_read" (which is an input and I pasted the timing report below). How do I make the timing analysis engine consider the port "p1750_hclk" as a clock? report_timing -from [get_port p1750_read]INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: max.INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUsINFO: [Timing 38-78] ReportTimingParams: -from_pins -max_paths 1 -nworst 1 -delay_type max -sort_by slack.Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.------------------------------------------------------------------------------------| Tool Version : Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015| Date : Mon Aug 21 16:31:01 2017| Host : athens.hdl-design.com running 64-bit CentOS release 6.9 (Final)| Command : report_timing -from [get_ports p1750_read]| Design : spock| Device : 7k325t-fbg900| Speed File : -1 PRODUCTION 1.12 2014-09-11------------------------------------------------------------------------------------Timing ReportSlack (MET) : 5.704ns (required time - arrival time) Source: p1750_read (input port clocked by clk_out3_clk_synthesizer_1 {rise@0.000ns fall@25.000ns period=50.000ns}) Destination: spock_emulation_inst/p1750_io_inst/p_read_reg/D (rising edge-triggered cell FDRE clocked by clk_out2_clk_synthesizer_1 {rise@0.000ns fall@6.250ns period=12.500ns}) Path Group: clk_out2_clk_synthesizer_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 50.000ns (clk_out2_clk_synthesizer_1 rise@50.000ns - clk_out3_clk_synthesizer_1 rise@0.000ns) Data Path Delay: 5.546ns (logic 0.728ns (13.125%) route 4.818ns (86.875%)) Logic Levels: 1 (IBUF=1) Input Delay: 42.500ns Clock Path Skew: 4.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.342ns = ( 13.842 - 12.500 ) Source Clock Delay (SCD): -2.898ns Clock Pessimism Removal (CPR): -0.135ns Clock Uncertainty: 0.321ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.396ns Phase Error (PE): 0.120ns Timing Exception: MultiCycle Path Setup -end 4 Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out3_clk_synthesizer_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y8 BUFG 0.000 0.000 r pclk_mb_to_ClockReset/O net (fo=2, routed) 2.180 2.180 ClockReset_inst/clk_synth_inst/inst/clk_in2 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT2) -5.078 -2.898 r ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT2 ------------------------------------------------------------------- ------------------- input delay 42.500 39.602 AJ9 0.000 39.602 r p1750_read (IN) net (fo=0) 0.000 39.602 p1750_read AJ9 IBUF (Prop_ibuf_I_O) 0.728 40.330 r p1750_read_IBUF_inst/O net (fo=3, routed) 4.818 45.148 spock_emulation_inst/p1750_io_inst/p1750_read_IBUF SLICE_X45Y187 FDRE r spock_emulation_inst/p1750_io_inst/p_read_reg/D ------------------------------------------------------------------- ------------------- (clock clk_out2_clk_synthesizer_1 rise edge) 50.000 50.000 r BUFGCTRL_X0Y8 BUFG 0.000 50.000 r pclk_mb_to_ClockReset/O net (fo=2, routed) 2.046 52.046 ClockReset_inst/clk_synth_inst/inst/clk_in2 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT1) -4.809 47.237 r ClockReset_inst/clk_synth_inst/inst/mmcm_adv_inst/CLKOUT1 net (fo=2, routed) 2.650 49.887 ClockReset_inst/clk_synth_inst/inst/clk_out2_clk_synthesizer BUFGCTRL_X0Y4 BUFGCTRL (Prop_bufgctrl_I0_O) 0.113 50.000 r ClockReset_inst/clk_synth_inst/inst/clkout2_buf/O net (fo=20304, routed) 1.342 51.342 spock_emulation_inst/p1750_io_inst/CK1750X4 SLICE_X45Y187 FDRE r spock_emulation_inst/p1750_io_inst/p_read_reg/C clock pessimism -0.135 51.207 clock uncertainty -0.321 50.886 SLICE_X45Y187 FDRE (Setup_fdre_C_D) -0.034 50.852 spock_emulation_inst/p1750_io_inst/p_read_reg ------------------------------------------------------------------- required time 50.852 arrival time -45.148 ------------------------------------------------------------------- slack 5.704 Lets solve this problem first then we can go onto the more challenging concerns. You may notice that the clock pointed to by the variable $hclk does not have any phase delay, for these reports I was using a run in which I removed the phase delay so I could play with it in the lab -- I do have this clock on "Enable Fine PS" control. I will be using your results and my lab results to further my analysis. Thanks in advance, Tom Tessier |
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我想使用端口“p1750_hclk”作为时序约束的参考时钟,如“p1750_lackn”和“p1750_read”(这是一个输入,我粘贴了下面的时序报告)。
如何让时序分析引擎将端口“p1750_hclk”视为时钟? 这很标准...... 您需要在FPGA的输出端口创建生成的时钟 create_generated_clock -name p1750_hclk -divide_by 1 -source [get_pins hclk_ODDR_inst / C] [get_ports hclk_p1750] 如果你的ODDR进行反转(D1连接到0而D2连接到1),那么你需要-invert标志 create_generated_clock -name p1750_hclk -divide_by 1 -invert -source [get_pins hclk_ODDR_inst / C] [get_ports hclk_p1750] 这定义了端口上的时钟。 现在,这个时钟可以(并且必须)用作指定set_output_delay约束的时钟 #HCLK - > LACKN设置= 15ns(电路板延迟低于18) #HCLK - > LACKN Hold = 13ns set_output_delay -clock [get_clocks p1750_hclk] -max 18.000 [get_ports p1750_lackn] set_output_delay -clock [get_clocks p1750_hclk] -min -13.000 [get_ports p1750_lackn] 不要使用-add_delay。 -min和a -max可以同时存在于引脚上 - -add_delay仅添加第二个最大值或第二个最小值(例如,对于DDR约束)。 Avrum 以上来自于谷歌翻译 以下为原文 I want to use the port "p1750_hclk" as my reference clock for the timing constraints like "p1750_lackn" and "p1750_read" (which is an input and I pasted the timing report below). How do I make the timing analysis engine consider the port "p1750_hclk" as a clock? This is pretty standard... You need to create a generated clock at the output port of the FPGA create_generated_clock -name p1750_hclk -divide_by 1 -source [get_pins hclk_ODDR_inst/C] [get_ports hclk_p1750] If your ODDR does inversion (the D1 is connected to 0 and the D2 is connected to 1), then you need the -invert flag create_generated_clock -name p1750_hclk -divide_by 1 -invert -source [get_pins hclk_ODDR_inst/C] [get_ports hclk_p1750] This defines the clock on the port. Now this clock can (and must) be used as the clock to specify the set_output_delay constraints # HCLK -> LACKN Setup = 15ns (18 below for board delay)# HCLK -> LACKN Hold = 13nsset_output_delay -clock [get_clocks p1750_hclk] -max 18.000 [get_ports p1750_lackn]set_output_delay -clock [get_clocks p1750_hclk] -min -13.000 [get_ports p1750_lackn]Don't use the -add_delay. A -min and a -max can exist on the pin at the same time - the -add_delay is only to add a second max or a second min (for example for a DDR constraint). Avrum |
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