如何解决Spartan-6时钟I / O引脚使用问题

应将单端时钟信号分配给P_GCLK。
另请看下面的帖子
此建议不适用于Spartan-6设备。
见图1-3至1-7的UG382。
图1-8似乎与之前的数字相矛盾，并表明N个输入是P输入的次要，也许有人可以详细说明这一点。
此建议（以及链接的线程）确实适用于Virtex-5器件。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
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在原帖中查看解决方案



以下为原文

Single ended clock signals should be assigned to P_GCLK.
Also have a look at below post
 
This advice does not apply to Spartan-6 devices.  See UG382 Figures 1-3 through 1-7.  Figure 1-8 seemingly contradicts the previous figures, and suggests that the N inputs are secondary to the P inputs, perhaps someone can elaborate on this.
 
This advice (and the linked thread) does apply to Virtex-5 devices.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.View solution in original post

...数据表“UG382第24页”，即“P和N输入遵循与时钟输入引脚上的标准输入相同的配置”，但我不知道此描述的含义。
让我重新说明一下：
P和N时钟输入对遵循与标准用户I / O差分对输入相同的配置规则。
换一种说法
用作时钟的差分对输入必须分配给要用作单个差分对的引脚对，不能使用“P”和“N”。
必须为输入引脚分配差分信号标准（例如LVDS25_25，TMDS_33等）
这有意义吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

... the datasheet "UG382 page 24" that is say "The P and N  inputs follow the same configuration as the standard inputs on the clock input pins", but I do not know the meaning of this description.
 
Let me re-phrase for clarity:

The P and N clock input pairs follow the same configuration rules as the standard user I/O differential pair inputs.
 
In other words

• differential pair inputs used as clocks must be assigned to pairs of pins intended to be used as a single differential pair, you cannot use use any "P" with any "N".
  

• you must assign a differential signaling standard to the input pins (e.g. LVDS25_25, TMDS_33, etc.)
  

Does this make sense?

 
-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

你好，先生：
好的，我理解，非常感谢
顺便说一句，如果时钟输入引脚是单端信号（例如LVCMOS25），我可以分配给P_GCLK还是N_GCLK？



以下为原文

Hi Sir:
ok, I understand,very thanks
 
btw, if clock input pin is single-end signal(e.g. LVCMOS25), can I assigned to either P_GCLK or N_GCLK？

应将单端时钟信号分配给P_GCLK。
另请看下面的帖子
此建议不适用于Spartan-6设备。
见图1-3至1-7的UG382。
图1-8似乎与之前的数字相矛盾，并表明N个输入是P输入的次要，也许有人可以详细说明这一点。
此建议（以及链接的线程）确实适用于Virtex-5器件。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Single ended clock signals should be assigned to P_GCLK.
Also have a look at below post
 
This advice does not apply to Spartan-6 devices.  See UG382 Figures 1-3 through 1-7.  Figure 1-8 seemingly contradicts the previous figures, and suggests that the N inputs are secondary to the P inputs, perhaps someone can elaborate on this.
 
This advice (and the linked thread) does apply to Virtex-5 devices.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

嗨先生：好的，非常感谢



以下为原文

Hi Sir:
ok, very thanks