SPARTAN-6 FPGA不支持ML605板

没有...
但你必须明白，Virtex和Spartan-6中的IDELAY / ODELAY之间存在显着差异。
在Virtex器件中（至少从Virtex-5开始 - 甚至可能是Virtex-4，我忘了）和7系列，IDELAY都经过校准。
这意味着每个可编程抽头的大小根据提供给IDELAYCTRL的参考时钟动态调整为固定的时间量 - 标称值为tREFCLK / 64（对于200MHz REFCLK约为78ps）。
在Spartan-6中，IDELAY分接头未经过校准，可以在很宽的范围内变化（基本上是硅器件在工艺，温度和电压方面的正常3：1变化）。
因此，在Virtex中实现使用校准的IDELAY / ODELAY实现高速接口的设计需要非常仔细地检查，以便将其移植到Spartan，并且根据边距，甚至可能不可能
以相同的比特率做。
Avrum
在原帖中查看解决方案



以下为原文

Nothing...
 
But you have to understand that there is a significant difference between the IDELAY/ODELAY in Virtex and in Spartan-6.
 
In Virtex devices (at least from Virtex-5 on - maybe even Virtex-4, I forget), and the 7 series, the IDELAY is calibrated. This means that the size of each programmable tap is dynamically adjusted to be a fixed amount of time based on the reference clock provided to the IDELAYCTRL - with the nominal value of tREFCLK/64 (around 78ps for a 200MHz REFCLK).
 
In the Spartan-6, the IDELAY taps are not calibrated and can vary over a very wide range (basically the normal 3:1 variation of silicon devices over process, temperature and voltage).
 
Therefore, a design that was implemented in a Virtex to implement a high speed interface using the calibrated IDELAY/ODELAY will need to be examined very carefully in porting it to a Spartan, and, depending on the margins, it may not even be possible to do at the same bitrate.
 
Avrum
View solution in original post

没有...
但你必须明白，Virtex和Spartan-6中的IDELAY / ODELAY之间存在显着差异。
在Virtex器件中（至少从Virtex-5开始 - 甚至可能是Virtex-4，我忘了）和7系列，IDELAY都经过校准。
这意味着每个可编程抽头的大小根据提供给IDELAYCTRL的参考时钟动态调整为固定的时间量 - 标称值为tREFCLK / 64（对于200MHz REFCLK约为78ps）。
在Spartan-6中，IDELAY分接头未经过校准，可以在很宽的范围内变化（基本上是硅器件在工艺，温度和电压方面的正常3：1变化）。
因此，在Virtex中实现使用校准的IDELAY / ODELAY实现高速接口的设计需要非常仔细地检查，以便将其移植到Spartan，并且根据边距，甚至可能不可能
以相同的比特率做。
Avrum



以下为原文

Nothing...
 
But you have to understand that there is a significant difference between the IDELAY/ODELAY in Virtex and in Spartan-6.
 
In Virtex devices (at least from Virtex-5 on - maybe even Virtex-4, I forget), and the 7 series, the IDELAY is calibrated. This means that the size of each programmable tap is dynamically adjusted to be a fixed amount of time based on the reference clock provided to the IDELAYCTRL - with the nominal value of tREFCLK/64 (around 78ps for a 200MHz REFCLK).
 
In the Spartan-6, the IDELAY taps are not calibrated and can vary over a very wide range (basically the normal 3:1 variation of silicon devices over process, temperature and voltage).
 
Therefore, a design that was implemented in a Virtex to implement a high speed interface using the calibrated IDELAY/ODELAY will need to be examined very carefully in porting it to a Spartan, and, depending on the margins, it may not even be possible to do at the same bitrate.
 
Avrum