Spartan 3a的时序问题代码该如何解决？

对不起，也许我太简化了。
FPGA从外部F-ram读取数据。
当读取完成时，更新脉冲发生1个时钟周期（在我的情况下为40 ns）Overvoltage_ack设置为“1”。
像这样的代码：
if（rising_edge（clk_25MHz））然后
if（read_update ='1'）然后
overvoltage_ack
DATA_IN
DATA_IN
if（overvoltage_ack ='1'）然后
overvoltage_ack：='0';
万一;

data_in 以下为原文

Sorry maybe I simplified it too much.
 
 
 
FPGA  reads data out of an external F-ram.  When the read is complete an update pulse happens for 1 clock cycle(40 ns in my case) Overvoltage_ack is set to '1'.
 
Code like this:
 
if(rising_edge(clk_25MHz)) then
 
if(read_update ='1') then
overvoltage_ack <= '1';
end if;
 
if(read_update2 = '1') then
powerlevel_ack <= '1';
end if;
 
case(STATE) is
when powerlevel_state =>
 
data_in <= X"00" & powerlevel_ack ;
if(powerlevel_ack ='1') then
powerlevel_ack ='0';
end if;
STATE <= WAIT_FOR_1SECOND;
 
when overvoltage_state =>
 
data_in <= X"00" & overvoltage_ack ;
if(overvoltage_ack ='1') then
overvoltage_ack ='0';
end if;
STATE <= WAIT_FOR_1SECOND;
 
end case;
 
 
end if;
 
Alright so I have a block ram and i Write to different addresses.  DATA_IN when I am writing the Powerlevel state will write a '1' in LSB if ACK is set high.   I am guessing that the Powerlevel_ack Flip flop is closer to the input of the Block ram?   When Overvoltage_ack is set to '1' and is in the overvoltage_state DATA_IN stays zero.  It as if  overvoltage_ack is a variable and  then sent to the DATA_IN.
 
Like this code:
 
 
when overvoltage_state =>
 
if(overvoltage_ack ='1') then
overvoltage_ack :='0';
end if;
data_in <= X"00" & overvoltage_ack ;
 
STATE <= WAIT_FOR_1SECOND;
 
I would expect this behavior:
 
Overvoltage_ack  is '1'
 
When rising edge happens:
Data_in becomes X"00" & '1';
Overvoltage_ack changes from '1' to '0';
 
Then when I come into this state again:
 
Overvoltage_ack is '0'
 
when rising edge happens:
 
Data_in becomes X"00" & '0';
Overvoltage_ack does not change.
 
I hope this explains it better.  Sorry if it is too simplified.  My code is very complex.  (This is what happens when you try to develop a product to SIL 4 safety level and designing all the filters and signal processing algorithms by hand :(.  We have no DSP slices and are not using Simulink/system generator.  We can't use a processor because than the project becomes twice the cost and harder to become SIL4.  This is just to share some safety fun! )
 

基本上：
过压状态在我的代码中每66.56 uSeconds发生一次。
发生更新事件并将overvoltage_ack设置为“1”;
然后

Data_in 以下为原文

Basically :
 
the overvoltage state Happens every 66.56 uSeconds in my code.  
 
Update event happens and sets overvoltage_ack to '1';
 
Then
 
Data_in <= X"00" & overvoltage_ack ;
if(overvoltage_ack ='1') then
overvotlage_ack <= '0';
end if;
 
Then it should write X"00" & '1' to the block ram and reset overvoltage_ack so that in 66.56 uSec it will write X"00"  & '0' to the block ram.  
 
Powerlevel state happens every 4.16 uSec.   
That is only difference in code.   
 

我没有模拟代码，因为它涉及从外部框架读取和写入以及通过我用另一个FPGA设计的uart进行通信。
我在6个月前模拟了通信，效果很好。
我有一个用户界面（旧学校3位7段显示），用于更改功率设置和过压容差。
更改设置时，会将值写入Fram。
这一切都很好，花花公子，直到我第二次尝试写。
对于功率设置，它工作正常，对于过压设置，它不接受第二个值。
这是因为Ack信号没有通过我的界面传输。
我的问题是：
如果您的块ram正在关闭CLK_A。
如果您的进程正在运行CLK_A。
如果你有这个if语句：
if（ACK ='1'）然后

DATA_IN 以下为原文

I have not simulated the code because it involves reading and writing from an external fram and communication over a uart i designed with another FPGA.    I simulated the Communications about 6 months ago and it works well. 
 
I have a user interface (Old school 3 digit 7 segment display) that is used to change power setting and and Overvoltage tolerance.  When a setting is changed it writes the value to the Fram. 
 
It all works fine and dandy until I try write a second time.  For the power setting it works fine, for the over voltage setting it doesn't accept a second value.  It is because the Ack signal is not being transmitted across my interface.
 


My question is this:
 
if your block ram is running off CLK_A.
 
if your process is running off CLK_A.
 
if you have this if statement:
 
if(ACK= '1') then

DATA_IN <= ACK;
ACK <= '0';
end if;
 
In what way can DATA_IN remain zero?  I.e.  somehow ACK is set zero before DATA_IN is set.
How can DATA_IN be '0'? How is that possible? 
 
Correct me if I am wrong, DATA_IN should be a snapshot of ACK?
 
So if I waited to turn on WE 3 clock cycles later it shouldn't matter?  DATA_IN is a register (flip flop in this example) and I dont' change the register for a long period of time.