如何在Spartan 3A上将频率从50 MHz降至20 MHz？

您可以将输入时钟运行到Spartan 3A中的DCM。
可能是最简单的方法
获得20 MHz将使用CLKDIV输出并将CLKDIV_DIVIDE设置为2.5
您也可以使用FX输出进行除法。
也可以除以
2.5使用没有DCM的逻辑，但通常会引入更多抖动，尤其是如果
输入时钟占空比不完全是50％。
无论您生成时钟，它都应由BUFG驱动到所有时钟负载
包括IOB将时钟提供给ADC。
使用DDR触发器
时钟C1，时钟条上的C2，D1接高电平，D2接低电平以产生时钟
在输出引脚上。
这提供了比尝试路由更清洁的时钟
时钟直接到垫子。
HTH，
的Gabor
-  Gabor
在原帖中查看解决方案



以下为原文

You can run the input clock to a DCM in the Spartan 3A.  Probably the easiest way
to get 20 MHz would be to use the CLKDIV output and set CLKDIV_DIVIDE to 2.5
You could also use the FX output to do the division.  It is also possible to divide by
2.5 using logic without a DCM, but that generally introduces more jitter, especially if
the input clock duty cycle is not exactly 50%.
 
However you generate the clock, it should be driven by a BUFG to all clock loads
including the IOB sourcing the clock to the ADC.  Use a DDR flip-flop with the
C1 on clock, C2 on clock bar, D1 tied high, and D2 tied low to generate the clock
on the output pin.  This provides a much cleaner clock than trying to route the
clock directly to the pad.
 
HTH,
Gabor
-- GaborView solution in original post

您可以将输入时钟运行到Spartan 3A中的DCM。
可能是最简单的方法
获得20 MHz将使用CLKDIV输出并将CLKDIV_DIVIDE设置为2.5
您也可以使用FX输出进行除法。
也可以除以
2.5使用没有DCM的逻辑，但通常会引入更多抖动，尤其是如果
输入时钟占空比不完全是50％。
无论您生成时钟，它都应由BUFG驱动到所有时钟负载
包括IOB将时钟提供给ADC。
使用DDR触发器
时钟C1，时钟条上的C2，D1接高电平，D2接低电平以产生时钟
在输出引脚上。
这提供了比尝试路由更清洁的时钟
时钟直接到垫子。
HTH，
的Gabor
-  Gabor



以下为原文

You can run the input clock to a DCM in the Spartan 3A.  Probably the easiest way
to get 20 MHz would be to use the CLKDIV output and set CLKDIV_DIVIDE to 2.5
You could also use the FX output to do the division.  It is also possible to divide by
2.5 using logic without a DCM, but that generally introduces more jitter, especially if
the input clock duty cycle is not exactly 50%.
 
However you generate the clock, it should be driven by a BUFG to all clock loads
including the IOB sourcing the clock to the ADC.  Use a DDR flip-flop with the
C1 on clock, C2 on clock bar, D1 tied high, and D2 tied low to generate the clock
on the output pin.  This provides a much cleaner clock than trying to route the
clock directly to the pad.
 
HTH,
Gabor
-- Gabor

有关ADC的一般说明， 
ADC采样时钟需要具有低抖动，以使ADC能够达到其最大值。
我似乎记得DCM上的一些输出并不特别“完全”，尤其是FX。
你真的需要20 MHz吗？
可以25 MHz做，更容易实现。



以下为原文

general note on ADCs,

  an ADC sample clock needs to be low jitter to let the ADC perform to it's maxim.
 
I seem to remember some of the outputs on the DCM are not particularly ' quite ', in particular the FX.
 
Do you really need 20 MHz ? could 25 MHz do , much easier to achieve.
 
 

我想你可以在电路板上使用20 MHz振荡器，并用它来为FPGA和ADC提供时钟。
然后在FPGA内部，您可以使用DCM将时钟提升至50 MHz。
-一个
----------------------------是的，我这样做是为了谋生。



以下为原文

I suppose you could use a 20 MHz oscillator on your board, and use it to clock both the FPGA and the ADC. Then inside the FPGA you can use a DCM to bring the clock up to 50 MHz.
 
-a
----------------------------Yes, I do this for a living.