设计资源可用于将设计转移到Spartan 3A系列？

的Gabor，
您使用的是标准xapp485设计文件吗？
您是否看过衍生S3A LVDS参考设计：
http://www.xilinx.com/products/boards/s3astarter/reference_designs.htm(Spartan-3A / 3AN入门套件电路板设计实例）
干杯，
BT



以下为原文

好吧，appnote没有提到3A入门套件，所以我使用的是标准文件。
从我所看到的，然而入门套件应用程序只有VHDL版本，但没有
平面图文件等。我想做的是在一个Spartan 3A（XC3S700A-4FG400C）中使用三个反序列化器。
此外，我将使用Camera Link的4位版本（28位数据）标准而不是5位
套件演示中的版本。
在这一点上，我正在尝试设计电路板，因此我需要一个可行的引脚和一些验证
三个解串器不会耗尽FPGA中的某些资源（时钟路由等）。
它看起来
就像反序列化器只使用一个DCM所以我认为这不会是一个问题。
我大多需要
请确保我没有将引脚锁定为无法使用的配置。
我目前使用标准appnote代码的问题是RLOC约束
似乎不适用于Spartan 3A，或者它们可能不适用于ISE 10.1.03，我没有
尝试使用ISE版本9.x
然而，入门套件appnote使用相同的硅（尽管在不同的封装中）
也许我会首先考虑那里的限制因素。
问候，
的Gabor
-  Gabor



以下为原文

Well, the appnote did not make any reference to the 3A starter kit, so I was using the standard files.
From what I can see, however the starter kit app only has the VHDL version, and doesn't have
floorplan files, etc.  What I'd like to do is use three deserializers in one Spartan 3A (XC3S700A-4FG400C).
Also I will be using the 4-bit version (28-bit data) standard for Camera Link rather than the 5-bit
version in the kit demo.
 
At this point I'm trying to get the board designed so I need a workable pinout and some verification
that three deserializers won't run out of some resource in the FPGA (clock routing, etc.).  It looks
like the deserializers uses only one DCM so I don't think that will be an issue.  Mostly I need to
be sure I don't lock the pins to an unusable configuration.
 
The problem I'm currently having with the standard appnote code is that the RLOC constraints
don't seem to work with Spartan 3A, or perhaps they don't work with ISE 10.1.03, I haven't
tried it with ISE version 9.x
 
However the starter kit appnote is using the same silicon (albeit in a different package) so
maybe I'll start by poring over the constraints there.
 
Regards,
Gabor
-- Gabor

Gabor，你最终在哪里结束了吗？
我在尝试使用4位RX和TX时遇到了类似的问题
设计在XCS3400A部件中。
到目前为止，我不得不通过映射器注释掉一些RLOC。
我有一些设计运行，但不是每个PAR运行。
我正在努力获得一致的时序收敛。



以下为原文

Gabor, where did you end up with this?  I am running into some similar problems trying to use the 4-bit RX and TX
designs in a XCS3400A part.  To date, I have had to comment out some of the RLOCs to make it through the mapper.
I have some design runs that work, but not every PAR run.  I am working to get consistent timing closure.

那个项目在我开始之后不久就被搁置了，所以我真的只有
就初步调查而言。
从你的描述来看，我猜
RLOC真的需要让设计工作，你会
需要找到合适的布局规划，以便在S3A中取代它
一致的结果。
您可能想联系您的FAE，看看您是否
可以得到这方面的帮助，因为它是一个值得原创的应用程序
appnote和S3A似乎是一个很好的候选人。
我确定
这种应用在Spartan-6中是不费脑子的，但是
Xilinx不能指望每个人都在等待最新的芯片来解决
他们存在的问题:)
-  Gabor



以下为原文

That project was set aside not long after I started it, so I really only got
as far as the initial investigation.  From your description, I'm guessing
the RLOC was really needed to make the design work and you would
need to find the right floorplanning to replace it in the S3A to get
consistent results.  You may want to contact your FAE to see if you
can get help with this, since it's an application worthy of the original
appnote and the S3A seems like a good candidate for this.  I'm sure
this sort of application would be a no-brainer in the Spartan-6, but
Xilinx can't expect everyone to wait for the latest silicon to solve
their existing problems :)
-- Gabor

谢谢回复。
我今天要参加FAE。
解决这个问题后，我会回复。



以下为原文

Thanks for the reply.  I am going to get an FAE involved today.  After I resolve this I will post back up.

我们在这方面取得了一些进展。
问题是LVDS TX和LVDS RX设计都使用通用的rloc和rloc_origins。
创建rloc时，默认组为hset。
所以我们使用rx和tx设计，你得到2个hset组。
您
需要为rx或tx设计创建一个hu_set，这样它们就不会都具有相同的默认hset组。
这解决了我的映射器问题。
现在我还在解决另一个问题，我的lvds rx数据引脚位于芯片的右侧
我的lvds rx时钟位于底部。
RLOC有所帮助，但我必须采取大的时钟插入延迟。
接下来旋转板子
将有更好的时钟位置。



以下为原文

We made some progress on this.  The problem is that both the LVDS TX and LVDS RX designs use generic rloc and rloc_origins.
When you create an rloc, the default group is a hset.  So we you use both the rx and tx designs, you get 2 hset groups.  You
need create a hu_set for the rx or tx design, so that they don't both have the same default hset group.
 
This solved my mapper problems.  Now I am still fighting another problem, my lvds rx data pins are on the right side of the chip
and my lvds rx clock is at the bottom.  The RLOCs help, but I have to take a big clock insertion delay.  Next spin of the board
will have better clock placement.