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我有一个使用3个PLL的LX45T设计。
简而言之,它们是: (1)Fvco = 800 MHz,使用bank 3中的MCB为400MHz DDR3 dRAM提供时钟; 它是由MIG产生的,除了输入是GCLK4(存储区1的下半部分)上的(单端)50 MHz时钟,我已经进行了必要的调整,还增加了200 MHz的全局时钟输出。 MIG实例化一个IBUFG,其输出直接连接到PLL(虽然我猜BUFIO2在那里被推断),并且也从包装器输出信号sys_clk_buf。 它还实例化BUFPLL_MCB。 (2)Fvco = 750 MHz,输出125 MHz和250 MHz全局时钟(我已经实例化了BUFG)以及750 MHz I / O时钟,我用它来对上半部分的125 Mb / s输入进行过采样 银行1,我已经实例化了BUFPLL (3)Fvco = 600 MHz,提供120 MHz全局时钟,我已经实例化了一个BUFG 如果我从sys_clk_buf中获取(2)和(3)中的一个,而从另一个全局时钟中获取另一个,则ISE很满意。 但是,如果我从sys_clk_buf中同时获取(2)和(3)它表示没有BUFPLL_MCB的站点,也没有(2)中的BUFPLL,并且“map”崩溃。 关于PLL连接的限制,ug382还不是很清楚,但我认为GCLK4可以通过BUFIO2_X4Y19连接两个PLL,另外两个通过BUFIO2_X3Y11连接(我没有使用GCLK8)。 也许BUFIO2需要实例化,还是什么? 以上来自于谷歌翻译 以下为原文 I've got a design in an LX45T that uses 3 PLLs. Briefly, they are: (1) Fvco = 800 MHz, sourcing clocks for a 400MHz DDR3 dRAM using the MCB in bank 3; it's as produced by the MIG except that the input is a (single-ended) 50 MHz clock on GCLK4 (bottom half of bank 1) and I've made the necessary adjustments and also added a 200 MHz global clock output. The MIG instantiates an IBUFG, the output of which is connected directly to the PLL (though I guess a BUFIO2 gets inferred there) and is also exported from the wrapper as signal sys_clk_buf. It also instantiates a BUFPLL_MCB. (2) Fvco = 750 MHz, sourcing 125 MHz and 250 MHz global clocks (for which I've instantiated BUFGs) and also a 750 MHz I/O clock which I use for oversampling some 125 Mb/s inputs in the top half of bank 1, and for which I've instantiated a BUFPLL (3) Fvco = 600 MHz, sourcing a 120 MHz global clock for which I've instantiated a BUFG ISE is happy with that if I source one of (2) and (3) from sys_clk_buf and the other from one of the global clocks. But if I source both (2) and (3) from sys_clk_buf it says there are no sites for the BUFPLL_MCB, nor for the BUFPLL in (2), and "map" crashes. ug382 isn't very clear about what the restrictions are for connections to PLLs, but I would have thought GCLK4 could connect to two PLLs through BUFIO2_X4Y19 and two more through BUFIO2_X3Y11 (I'm not using GCLK8). Maybe the BUFIO2s need to be instantiated, or something? |
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建议您使用BUFG缓冲区缓冲50MHz输入时钟,并使用BUFG输出作为所有PLL的时钟输入。
- 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 Suggest you buffer the 50MHz input clock with a BUFG buffer, and use the BUFG output as clock input to all PLLs. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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