无法将PLL输出路由到bank 2-bank 0工作

我的问题来自bank 1的差分时钟（PinIO_L40P_GCLK11_1 / IO_L40N_GCLK10_1）通过IODELAY和BUFIO路由到PLL。
问题：xilinx ISE不允许我将输出信号路由到bank 2（原理图中的变体B） -  bank 0（原理图中的变体A）工作正常。
变体B将导致错误消息（见下文）。
额外的BUFG没有帮助（只有全局路由问题）。
错误：位置：1238  - 组件“XLXI_52 / PLL_ADV”没有可行的站点。
该组件有6个可能的位置：位置“PLL_ADV_X0Y0”由于以下条件而无法用于放置组件：错误：放置：1201  -  PLL类型的组件不可放置，因为它具有放置在区域中的锁定负载：
CLOCKREGION_X0Y0。
存在一个限制，即PLL的时钟负载必须位于PLL的水平相邻时钟区域。
建议将BUFG用于此时钟信号，以便将时钟负载放置在器件的任何位置。
如果时钟驱动器或时钟负载被锁定或区域分组，请确保它们被约束到水平相邻的时钟区域。由于跟随误差条件，位置“PLL_ADV_X0Y1”不能用于放置组件：错误：放置：1201  -
PLL类型的组件不可放置，因为它具有放置在区域中的锁定负载：CLOCKREGION_X0Y0。
存在一个限制，即PLL的时钟负载必须位于PLL的水平相邻时钟区域。
建议将BUFG用于此时钟信号，以便将时钟负载放置在器件的任何位置。
如果时钟驱动器或时钟负载被锁定或区域分组，请确保它们被约束到水平相邻的时钟区域。第4.2节架构特定功能的初始放置（校验和：c263894c）实时：7秒完成Placer完成的总实时时间：
7秒Placer完成的总CPU时间：7秒ERROR：Pack：1654  - 时序驱动的放置阶段遇到错误。
感谢帮助



以下为原文

My Problem

A differential clock from bank 1 (PinIO_L40P_GCLK11_1/ IO_L40N_GCLK10_1) is routed via IODELAY and BUFIO to a PLL.
Problem: xilinx ISE does not let me route the output signal to bank 2 (Variant B in the schematic) - bank 0 (Variant A in the schematic) works fine.
Variant B will cause the error message (see below). Additional BUFG does not help (only a global routing problem).


ERROR:Place:1238 - Component "XLXI_52/PLL_ADV" does not have a feasible site.
   There are 6 potential locations for the component:

Location "PLL_ADV_X0Y0" cannot be used to place the component due to following
error condition(s):

ERROR:Place:1201 - Component of type PLL is not placeable
   because it has locked loads placed in regions: CLOCKREGION_X0Y0.
   There is a restriction that the clock loads of a PLL must be in a
   horizontally adjacent clock region to the PLL. It is recommended that a BUFG
   be used for this clock signal so that the clock loads can be placed anywhere
   on the device. If the clock driver or clock loads are locked or area grouped,
   please ensure that they are constrained to horizontally adjacent clock
   regions.

Location "PLL_ADV_X0Y1" cannot be used to place the component due to following
error condition(s):

ERROR:Place:1201 - Component of type PLL is not placeable
   because it has locked loads placed in regions: CLOCKREGION_X0Y0.
   There is a restriction that the clock loads of a PLL must be in a
   horizontally adjacent clock region to the PLL. It is recommended that a BUFG
   be used for this clock signal so that the clock loads can be placed anywhere
   on the device. If the clock driver or clock loads are locked or area grouped,
   please ensure that they are constrained to horizontally adjacent clock
   regions.
Phase 4.2  Initial Placement for Architecture Specific Features
(Checksum:c263894c) REAL time: 7 secs

Total REAL time to Placer completion: 7 secs
Total CPU  time to Placer completion: 7 secs
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.


Thanks for help

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