转移IOCLK而不是使用IODELAY2

是的，PLL_ADV plusBUFPLL是一个很好的时钟解决方案 - 高达1080 Mbps（-3）SDR，并且正确生成SERDESSTROBE。
但请注意以下几点：
* PLL_ADV重新配置文档记录不清，有点乱 - 请参阅xapp879了解所涉及的内容。
*修改阶段后需要重置PLL_ADV，然后在输入阶段跳转后等待BUFPLL重新建立锁相。
在BUFPLL重新建立锁定之前，SERDESSTROBE将无法正常工作。
* PLL_ADV相位变化具有1/8 VCO频率的最小步长，因此对于1GHz操作，最精细的步长为125 ps，对于较低的VCO频率，较粗的步长
当使用正确的PLL_ADV plusBUFPLL加BUFG加上ISERDES2电路时，您的要点＃1和＃2不应该成为问题，如UG382图1-16“基本PLL ISERDES2（SDR）”所示。
在最高速度下，ISERDES2的平行侧的设置和保持可能会有些紧张，但时间报告将指导您。
根据需要添加额外的缓冲FF。
-  Stephen EcobSilicon On InspirationSydney Australiawww.sioi.com.au $ 49 Spartan 6主板配32MB DDR DRAM？http：//www.sioi.com.au/shop/product_info.php/products_id/47



以下为原文

Yes,  PLL_ADV plus BUFPLL make a great clocking solution - works up to 1080 Mbps (-3) SDR and SERDESSTROBE is generated correctly for you.
 
Be aware of a few things though:
 
* PLL_ADV reconfiguration is poorly documented and a bit messy - see xapp879 for what's involved.
 
* You'll need to reset the PLL_ADV after modifying the phase and then wait for the BUFPLL to reestablish phase lock after the input phase jumps. SERDESSTROBE will not work correctly until BUFPLL reestablishes lock.
 
* PLL_ADV phase changes have a smallest step of 1/8 VCO frequency, so the finest possible step is 125 ps for 1GHz operation, coarser for lower VCO frequencies
 
Your points #1 and #2 should not be a concern when using the correct PLL_ADV plus BUFPLL plus BUFG plus ISERDES2 circuit as shown in UG382 Figure 1-16 "Basic PLL ISERDES2 (SDR)".  Set up and hold for the parallel side of the ISERDES2 can be somewhat tight at the highest speeds, but the timing reports will guide you.  Add extra buffering FFs as needed.
 
--
Stephen Ecob
Silicon On Inspiration
Sydney Australia
www.sioi.com.au
$49 Spartan 6 board with 32MB DDR DRAM ?
http://www.sioi.com.au/shop/product_info.php/products_id/47
 

感谢您的精确，但我主要担心的是IOCLK和CLKDIV之间的对齐（阶段）。
我相信这些时钟应该对齐BUFPLL / ISERDES2电路才能正常工作，但我不知道我能用多少电路来移动/取消它们仍然正常工作。



以下为原文

Thank you for the precisions, but my main concern was about the alignment (phase)  between IOCLK and CLKDIV. I believe these clocks should be aligned for the BUFPLL/ISERDES2 circuit to work correctly, but I do not know by how much I can shift/de-align them with the circuit still working.

我在这里知识的边界，所以我不确定我的答案将是100％正确的。
我目前的项目使用的是我们正在讨论的电路类型，但该项目仅处于早期RTL开发阶段，因此我正在积极学习该领域。
阅读UG382（v1.6）pp53-55，在我看来，如果你使用p33图1-16所示的电路，那么BUFPLL将产生与CLKDIV处于良好相位的IOCLK和SERDESSTROBE信号。
在此之后，如果您动态重新编程PLL_BASE输出CLKOUT0和CLKOUT1的相位然后复位PLL_BASE，那么我假设BUFPLL将进行调整，以便一旦BUFPLL LOCK信号被置位，那么将建立一组新的良好相位。
所以，是的，IOCLK和CLKDIV之间的相位对齐需要正确，ISERDES2才能正常工作，但我认为如果你使用图1-16的电路，BUFPLL会自动为你做。
当你说“我可以在电路仍在工作时移动/取消对齐多少”时，我相信答案是BUFPLL可以防止它们被取消对齐，其目的是始终保持它们正确对齐。
是否有意义 ？
斯蒂芬



以下为原文

I'm at the boundary of my knowledge here, so I am not certain my answers will be 100% correct. 
 
My current project uses the type of circuit we're talking about, but the project is only in the early RTL development stages, so I am actively learning in this area.
 
Reading UG382 (v1.6) pp53-55, it seems to me that if you use the circuit shown on p33 Figure 1-16 then the BUFPLL will generate IOCLK and SERDESSTROBE signals that are in good phase with CLKDIV.
 
After this, if you dynamically reprogram the phase of PLL_BASE outputs CLKOUT0 and CLKOUT1 and then reset the PLL_BASE then I assume the BUFPLL will adjust so that once the BUFPLL LOCK signal is asserted then a new set of good phases will be established.
 
So yes, the phase alignment between IOCLK and CLKDIV needs to be correct for the ISERDES2 to work correclty but I think that the BUFPLL will automatically do that for you, if you use the circuit of Figure 1-16.
 
When you say "how much can I shift/de-align them with the circuit still working", I believe that the answer is that the BUFPLL prevents them from being de-aligned at all, its purpose is to always keep them properly aligned.
 
Does it make sense ?
 
Stephen
 
 

塞巴斯蒂安（和斯蒂芬），
打开webcase并使用Xilinx应用程序支持并不羞耻，特别是在文档可能含糊不清或不完整的情况下。
像我们这样的人为Xilinx应用团队成员提供了一些工作保障。
他们取决于我们！
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Sebastien (and Stephen),
 
There is no shame in opening a webcase and using Xilinx apps support, particularly where the documentation may be ambiguous or incomplete.
 
It is people like us who provide some bit of job security to the Xilinx apps team members.  They are depending on us!
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

BUFPLL（$ XILINX / verilog / src / unisims / BUFPLL.v）的仿真模型只是连接PLLIN-> IOCLK，因此除非该模型也不完整，否则PLL_ADV阶段的改变将导致IOCLK的移位。
@Bob：我以为他们也在这个论坛上？



以下为原文

The simulation model for BUFPLL ($XILINX/verilog/src/unisims/BUFPLL.v) simply connects PLLIN->IOCLK, so unless that model is incomplete too, a change in the PLL_ADV phase would result in a shift of IOCLK.
 
@Bob: I thought they were on this forum too?
 

@Bob：我以为他们也在这个论坛上？
也许是的，也许不，取决于可用的时间和倾向，是我的理解。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

@Bob: I thought they were on this forum too?
 
Maybe yes, maybe no, depending on time available and inclination, is my understanding.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

我的猜测是模拟模型不完整。
正如Bob建议的那样，获得一个好答案的最佳机会是打开一个webcase。



以下为原文

My guess is that the simulation model is incomplete.
As Bob has suggested, your best chance of getting a good answer is to open a webcase.
 

完成，webcase号码是910418。



以下为原文

Done, webcase number is 910418.