将BUFIO2模块输出连接到IODELAY2模块时出错

你好
在探索loc解决方案之前，在这里讨论BUFIO2和IODELAY2的用法是什么？
GCLK输入应该直接驱动两个BUFIO2。
使用两个BUFIO2，其中第一个BUFIO2（USE_DOUBLER）用于C0，反向时钟使用BUFIO2（I_INVERT = TRUE）用于连接到同一GCLK的C1。
FPGA逻辑由BUFG（C0 BUFIO2-DIVCLK）驱动。
通过BUFG存在路由延迟。•使用IODELAY2需要IBUFGDS_DIFF_OUT。
（参见图1-35，第49页）•不支持带IODELAY2的单端输入。
您必须找出IOB属于哪个区域的位置。
据此，您相应地找到相应的区域BUFIO2和IODELAY2。
INST“lvdss2p_inst / bufio2_inv_inst”LOC = BUFIO2_X3Y1; // BR中的BUFIO2
所有指南都列在以下文档中：
http://www.xilinx.com/support/documentation/user_guides/ug382.pdf



以下为原文

Hi 
Before you explore the loc solution, whats the usage of BUFIO2 AND IODELAY2 here?
The GCLK input should directly drive two BUFIO2s. Use two
BUFIO2s with the first BUFIO2 (USE_DOUBLER) for C0 and an inverted clock using
BUFIO2 (I_INVERT = TRUE) for C1 connected to the same GCLK. FPGA logic is
driven by BUFG (C0 BUFIO2-DIVCLK). There is a routing delay through the BUFG.
• Using an IODELAY2 requires the IBUFGDS_DIFF_OUT. (See Figure 1-35,
page 50)
• A single-ended input with IODELAY2 is not supported.
 
You have to find out where the IOBs belong to as in which region. According to that you loc the corresponding region BUFIO2 and IODELAY2 accordingly.
 
INST "lvdss2p_inst/bufio2_inv_inst" LOC = BUFIO2_X3Y1;//the BUFIO2 in BR
 
All the guidelines are listed in the following document:
http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

嗨，
您可以使用以下约束将IODELAY / BUFIO2组件锁定到同一半库
INST“BUFIO2_1_NonInvert”LOC = BUFIO2_XxYy;
你是针对斯巴达-6？
如是，
有八个BUFIO2区域，每个区域有4个BUFIO2。
BUFIO2只能驱动一组（IDDR / IODELAY）IOB。
可以由BUFIO2驱动的IOB列于http://www.xilinx.com/support/documentation/user_guides/ug385.pdf的第28页中。
以下是八个BUFIO2区域的列表。
您需要检查IODELAY连接到哪个IOB，然后检查IOB落在哪个区域（来自UG）。
然后，您可以将BUFIO2实例锁定到相应区域中的BUFIO2站点。
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi,
 
You can lock the IODELAY/BUFIO2 components to same half bank using below constraints
 
INST "BUFIO2_1_NonInvert " LOC = BUFIO2_XxYy;
 
Are you targetting spartan-6?
 
If yes, 
There are eight BUFIO2 regions, each with 4 BUFIO2. A BUFIO2 can drive only a set of (IDDR/IODELAY)IOB’s. The IOB’s which can be driven by a BUFIO2 are listed in page-28 of http://www.xilinx.com/support/documentation/user_guides/ug385.pdf
 
Below is the list of eight BUFIO2 regions.

 
You need to check to which IOB this IODELAY is connected and then in which region the IOB falls (from the UG). you can then lock the BUFIO2 instance to the BUFIO2 site in the corresponding region.
 
Thanks,
Deepika.
Thanks,
Deepika.
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以下是除上述帖子之外的更多信息
此错误消息（错误：位置：1286）不仅指向连接到BUFIO2的IODELAY，还可以在BUFIO2 IOCLK引脚连接到非IO原语时报告。
IOCLK只应用于驱动IO原语，例如IDDR2。
如果您看到此错误消息并且您没有使用IODELAY或不确定为什么会发生，请确保您已在设计中正确连接BUFIO2中的IOCLK。
如果您希望在整体设计中使用BUFIO2中的clk，则必须通过BUFG使用DIVCLK并使用全局时钟资源。
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以下为原文

The below is some more information in addition to the above posts
 
This error message (ERROR:Place:1286) does not only refer to IODELAYs connected to BUFIO2s, it can also be reported any time the BUFIO2 IOCLK pin is connected to a non IO primitive. The IOCLK should only be used to drive IO primitives, like for example IDDR2.

If you see this error message and you are not using IODELAYs or are unsure why it occurs, please ensure you have connected the IOCLK from the BUFIO2 correctly in your design. If you wish to use a clk from the BUFIO2 in your overall design it is necessary to use the DIVCLK through a BUFG and use the global clock resources.


 
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>错误：位置：1286  -  Placer检测到BUFIO2组件>驱动组件（引脚上）
错误消息表明您已将BUFIO2的输出连接到IODELAY2元素的IDATAIN端口。
IDATAIN端口只能由IBUF / IBUFDS输入驱动，BUFIO2只能连接到IDDR / ODDR / ISERDES / OSERDES元件的时钟端口。
您需要修复HDL代码。
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以下为原文

> ERROR:Place:1286 - Placer has detected a BUFIO2 component < BUFIO2_1_NonInvert >
> driving component < IODELAY2_DCLKa_C0 > (on pin < IDATAIN >)
 
The error message indicates that you have connected the output of the BUFIO2 to the IDATAIN port of the IODELAY2 element.   The IDATAIN port can only be driven by an IBUF/IBUFDS input and the BUFIO2 can only connect to the clock ports of the IDDR/ODDR/ISERDES/OSERDES elements.
 
You need to fix your HDL code.
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