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在“Spartan-6 FPGA数据手册:DC amd开关特性”之后,IODELAY2元件Spartan6的最大延迟定义为: 最大延迟=整数(抽头数/ 8)X Ttap8 + Ttapn。 因此,如果速度等级为3的Spartan6具有下一个最大延迟时间: Ttap1 = 8 ps Ttap2 = 40 ps Ttap3 = 95 ps Ttap4 = 108 ps Ttap5 = 171 ps Ttap6 = 207 ps Ttap7 = 212 ps Ttap8 = 292 ps 如果IODELAY2元素有参数IDELAY_VALUE = 2那么我正在等待IODELAY2的最大延迟: 整数(2/8)X Ttap8 + Ttap2 = 0 X Ttap8 + Ttap2 = 0 X 292 ps + 40 ps = 40 ps。 但是在P'n'R跟踪后给我的值为tioddo_IDATAIN = 2.128 ns, Coregen计算延迟为2.925 ns, ISIM在行为模拟中显示延迟约130 ps 老实说我对这种结果的分散感到困惑, 我的问题是:“有人知道如何预测/计算这种延迟” 第二个问题是: “有人知道SIM_TAPDELAY_VALUE参数是什么意思(但请不要引用数据表中的参数描述 - 我读过这个但我现在还不清楚)” 先谢谢你 Motspan Viktor 以上来自于谷歌翻译 以下为原文 Dear Sirs! Following "Spartan-6 FPGA Data Sheet: DC amd switching Characteristics" the maximum delay of IODELAY2 element Spartan6 is defined as: Maximum delay = integer(number of taps/8) X Ttap8 + Ttapn. So, if Spartan6 with speed grade -3 have the next maximum delays for taps: Ttap1 = 8 ps Ttap2 = 40 ps Ttap3 = 95 ps Ttap4 = 108 ps Ttap5 = 171 ps Ttap6 = 207 ps Ttap7 = 212 ps Ttap8 = 292 ps and if IODELAY2 element have parameter IDELAY_VALUE=2 then I am awaiting maximum delay of IODELAY2 as: integer(2/8) X Ttap8 + Ttap2 = 0 X Ttap8 + Ttap2 = 0 X 292 ps + 40 ps = 40 ps. But after P'n'R trace give me value of Tioddo_IDATAIN = 2.128 ns, Coregen calculate delay as 2.925 ns, ISIM shows in behavioral simulation delay about 130 ps Honestly say I am really confused by such dispersion in results, and my question is: "Does someone know how to predict/calculate this delay" And second question is: "Does someone know what does SIM_TAPDELAY_VALUE parameter mean (but please do not quote parameter description from datasheet - I read this but it is still not clear for me)" Thank you in advance Motspan Viktor |
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6个回答
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有没有方法在设计阶段估计这种延迟?
IODELAY2的固有延迟不如使用IO的建立和保持分析那么重要。 由于建立/保持是过程电压和温度(PVT)的多维问题,因此只能通过定时分析仪来完成。 如果单个原始数字对您仍然很重要,那么您已经掌握了指针(2.128 nS - 40pS = 2.088nS),然后您可以应用数据表中的增量延迟。 请记住,IODELAY2未校准,并且在最小和最大延迟之间会有非常宽的延迟变化。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Is there method to estimate this delays at design phase? The intrinsic delay of the IODELAY2 isn't as important as the setup and hold analysis of the IO that uses. Since the setup/hold is a multi-dimension problem across Process Voltage and Temperature (PVT) this can only be done by the timing analyzer. If a single raw number is still important to you then you have already have that at your finger tips (2.128 nS - 40pS = 2.088nS) and then you can apply the incremental delays from the datasheet. Please remember that the IODELAY2 is not calibrated and it will have a very wide delay variation between min and max delays. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.comView solution in original post |
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最近Spartan-6速度文件发生了变化(延迟改进),所以你应该使用ISE 12.4来获得-3速度等级的正确定时。
如果您使用的是此版本的软件,则报告的数字是真实正确的数字。 您所指的数据表条目仅用于每次点击的增量延迟,并且不包括进入IODELAY2块的基本延迟。 来自CoreGen的任何东西(我不清楚它来自哪里)只是一个估计。 行为仿真中的ISIM很可能只使用增量抽头延迟,但这并不是真正可用的,因为你不会有所有其他延迟(时钟和数据路径)。 SIM_TAPDELAY_VALUE是模拟期间每个TAP将使用的延迟值(以皮秒为单位)。 如果将其设置为10并且将IDELAY2_VALUE设置为20,那么它将具有200pS的延迟。 如果将其设置为50并且将IDELAY2_VALUE设置为20,那么它将具有500pS的延迟。 IODELAY2未校准,并且在最小值和最大值之间有很宽的范围。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 There have been recent changes in the Spartan-6 speed file (delay improvements) so you should be using ISE 12.4 for correct timing with the -3 speed grade. If you are using this version of the software than the reported number is the true and correct number. The data sheet entry that you are referring to is only for the incremental delay per-tap and does not include the basic delay to get in to and of the IODELAY2 block. Anything from CoreGen (it isn't clear to me where this is even coming from) is an estimate only. ISIM in behavioural simulation is likely only using a incremental tap delay, but this is not really usable anyway as you won't have all of the other delays (clock and data paths) either. SIM_TAPDELAY_VALUE is the delay value in picoseconds that will be used per TAP during simulation. If this is set to 10 and the IDELAY2_VALUE is set to 20 then it would have 200pS of delay. If this is set to 50 and the IDELAY2_VALUE is set to 20 then it would have 500pS of delay. The IODELAY2 is not calibrated and it has a wide range between the minimum and maximum. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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是的我正在使用ISE12.4和最后的speedfiles升级。
那么,实际值只能通过TRACE访问,而且没有方法可以在设计阶段估算这种延迟? 以上来自于谷歌翻译 以下为原文 Yes I am using ISE12.4 with last speedfiles upgrade. So, actual values only accesible through the TRACE, and no method to estimate this delays at design phase? |
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那么,实际值只能通过TRACE访问,而且没有方法可以在设计阶段估算这种延迟?
这对于IODELAY2来说是正确的,因为它与FPGA的所有其他元素一样。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 So, actual values only accesible through the TRACE, and no method to estimate this delays at design phase? This is true for the IODELAY2 as it is with all of the other elements of the FPGA. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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谢谢你的回答,你是非常有帮助的,但问题的第二部分呢:
有没有方法在设计阶段估计这种延迟? 以上来自于谷歌翻译 以下为原文 Thank you for answers, you are very helpful but what about second part of question: Is there method to estimate this delays at design phase? |
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有没有方法在设计阶段估计这种延迟?
IODELAY2的固有延迟不如使用IO的建立和保持分析那么重要。 由于建立/保持是过程电压和温度(PVT)的多维问题,因此只能通过定时分析仪来完成。 如果单个原始数字对您仍然很重要,那么您已经掌握了指针(2.128 nS - 40pS = 2.088nS),然后您可以应用数据表中的增量延迟。 请记住,IODELAY2未校准,并且在最小和最大延迟之间会有非常宽的延迟变化。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 Is there method to estimate this delays at design phase? The intrinsic delay of the IODELAY2 isn't as important as the setup and hold analysis of the IO that uses. Since the setup/hold is a multi-dimension problem across Process Voltage and Temperature (PVT) this can only be done by the timing analyzer. If a single raw number is still important to you then you have already have that at your finger tips (2.128 nS - 40pS = 2.088nS) and then you can apply the incremental delays from the datasheet. Please remember that the IODELAY2 is not calibrated and it will have a very wide delay variation between min and max delays. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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