请问我可以在时钟线上放置一个IODELAY2元素吗？

它的时序余量是足够的，充分已知，并且数据速率足够低，然后数据输入上的静态IDELAY2块可以工作（例如DEFAULT模式）。
如果时序余量太紧或数据速率对于静态延迟设置来说太高，则动态的每通道延迟可以起作用。
这需要恒定的时钟源，偶尔重新校准输入延迟块（例如DIFF_PHASE_DETECTOR模式）。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

It timing margins are sufficient, sufficiently known, and data rates are low enough, then static IDELAY2 blocks on data inputs can work (e.g. DEFAULT mode).
 
If timing margins are too tight or data rates are too high for static delay-setting, then the dynamic per-channel delays can work.  This requires a constant clock source, and occasional re-calibration of the input delay blocks (e.g. DIFF_PHASE_DETECTOR mode).
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

eteam00写道：
它的时序余量是足够的，充分已知，并且数据速率足够低，然后数据输入上的静态IDELAY2块可以工作（例如DEFAULT模式）。
如果时序余量太紧或数据速率对于静态延迟设置来说太高，则动态的每通道延迟可以起作用。
这需要恒定的时钟源，偶尔重新校准输入延迟块（例如DIFF_PHASE_DETECTOR模式）。
- 鲍勃埃尔金德
ADC时钟输出为100 MHz。
Dunno，如果那个“太高了”。
除转换器输出时钟外，FPGA还具有全局100 MHz时钟，该时钟始终可用，可用于校准。
该100 MHz时钟也作为其“编码器”时钟输入驱动到转换器。
转换器将其缠绕并驱动输出时钟（返回FPGA），延迟时间可在1.1到3.2 ns之间变化。
转换器还通过输入时钟的延迟驱动数据位，输出时钟介于1 ns和2.7 ns之间。
因此输出时钟基本上与数据重合或略微超前。
但它也倒置了。
而现在我更困惑了。
但我仍然认为简单地将时钟延迟半个时间（DDR为2.5 ns）就可以实现我想要的效果。
延迟一个信号比延迟八个更容易，这就是为什么我想知道我是否能真正做到这一点 - 时钟输入线上的IODELAY2。
我正在仔细阅读数据表的SelectIO部分。
----------------------------是的，我这样做是为了谋生。



以下为原文

eteam00 wrote:
It timing margins are sufficient, sufficiently known, and data rates are low enough, then static IDELAY2 blocks on data inputs can work (e.g. DEFAULT mode).
 
If timing margins are too tight or data rates are too high for static delay-setting, then the dynamic per-channel delays can work.  This requires a constant clock source, and occasional re-calibration of the input delay blocks (e.g. DIFF_PHASE_DETECTOR mode).
 
-- Bob Elkind

The ADC clock output is 100 MHz. Dunno if that's "too high." 
 
The FPGA has, in addition to the converter output clocks, a global 100 MHz clock that is always available and could possibly be used for the calibration. That 100 MHz clock is also driven out to the converters as their "encoder" clock input. The converter wraps that around and drives the output clock (back to the FPGA) with a delay that can vary from 1.1 to 3.2 ns. The converter also drives the data bits out with a delay from the input clock of between 1 ns and 2.7 ns.
 
So the output clock occurs essentially coincident with, or slightly ahead, of the data.
 
But it's also inverted. And now I'm more confused. but I still think that simply delaying the clock by half a bit time (2.5 ns for DDR) will do what I want. And delaying one signal is easier than delaying eight, which is why I wonder if I can actually do that -- IODELAY2 on the clock input line.
 
I am carefully rereading the SelectIO part of the data sheet.
----------------------------Yes, I do this for a living.

我正在仔细阅读数据表的SelectIO部分。
另请阅读UG381，从第70页开始的部分（版本1.4）。
动态输入延迟模式设计用于由于（可变）偏斜而导致采样时钟和单个输入数据之间的相位关系未知（或不可知）的应用。
此描述适用于HDMI输入（没有任何规格用于通道匹配），并且似乎也适合您的多通道，多ADC输入。
延迟一个信号比延迟八个更容易，这就是为什么我想知道我是否能真正做到这一点 - 时钟输入线上的IODELAY2。
不要忘记这个格言：FPGA已经完全购买并付费 - 在8个输入数据上使用8个延迟而不是在时钟上延迟1个延迟。
使用每通道延迟可以实现每通道去偏移，这意味着额外的时序余量。
ADC时钟输出为100 MHz。
Dunno，如果那个“太高了”。
Phhfffft！
每通道数据速率是100Mb /秒（SDR）还是200Mb /秒（DDR）？
如果使用输入数据的源同步采样，则需要将ADC输入通道和时钟组合到BUFIO区域中。
然后，当从多个输入时钟域跨越到单个系统时钟域时，您需要协调ADC-ADC偏移。
如果使用动态输入延迟模式，则每个输入通道动态对齐前端的系统时钟。
这不是免费午餐，因为每个输入通道可能以完整采样时钟（位）周期的增量彼此错位。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

I am carefully rereading the SelectIO part of the data sheet.
 
Also read UG381, section  beginning on page 70 (version 1.4).
 
The dynamic input delay modes are designed for applications where the phase relationship between sampling clock and individual input data is unknown (or unknowable) because of (variable) skews.  This description applies to HDMI inputs (no specification whatsoever for channel matching), and seems to fit your multi-channel, multi-ADC inputs as well.
 
And delaying one signal is easier than delaying eight, which is why I wonder if I can actually do that -- IODELAY2 on the clock input line.
 
Don't  forget the maxim:  the FPGA is already fully bought and paid for -- it costs no more to use 8 delays on 8 input data than 1 delay on the clock.  Using per-channel delay give you per-channel de-skewing, which means additional timing margin.
 
The ADC clock output is 100 MHz. Dunno if that's "too high."
 
Phhfffft!  Is per-channel data rate 100Mb/sec (SDR) or 200Mb/sec (DDR) ?
 
If you use source-synchronous sampling of input data, you need to group ADC input channels and clocks together into BUFIO regions.  Then you need to reconcile ADC-ADC skews when crossing from multiple input clock domains(s) to single system clock domain.
 
If you use the dynamic input delay mode, each input channel is dynamically aligned to the system clock at the front end.  This isn't a free lunch, as each input channel may be mis-aligned to each other in increments of a full sampling clock (bit) period.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

eteam00写道：
我正在仔细阅读数据表的SelectIO部分。
另请阅读UG381，从第70页开始的部分（版本1.4）。
动态输入延迟模式设计用于由于（可变）偏斜而导致采样时钟和单个输入数据之间的相位关系未知（或不可知）的应用。
此描述适用于HDMI输入（没有任何规格用于通道匹配），并且似乎也适合您的多通道，多ADC输入。
每个转换器都提供自己的时钟，因此所有转换器的输出都与其时钟同步。
所有八个转换器基本上是独立的
所以转换器之间的偏差是无趣的。
延迟一个信号比延迟八个更容易，这就是为什么我想知道我是否能真正做到这一点 - 时钟输入线上的IODELAY2。
不要忘记这个格言：FPGA已经完全购买并付费 - 在8个输入数据上使用8个延迟而不是在时钟上延迟1个延迟。
使用每通道延迟可以实现每通道去偏移，这意味着额外的时序余量。
是的，注意到。
我在寻找“最简单的”。
就像“最容易理解”和“最容易上班”一样。
ADC时钟输出为100 MHz。
Dunno，如果那个“太高了”。
Phhfffft！
每通道数据速率是100Mb /秒（SDR）还是200Mb /秒（DDR）？
如果使用输入数据的源同步采样，则需要将ADC输入通道和时钟组合到BUFIO区域中。
然后，当从多个输入时钟域跨越到单个系统时钟域时，您需要协调ADC-ADC偏移。
它是200 Mb /秒DDR，因此是100 MHz时钟。
我第一次完成数据捕获和后续处理似乎可以满足时间要求。
而且似乎这些工具只是将时钟放在BUFG上，所以它没有什么比这更好的了。
但这并没有解决延迟问题，尽管我的约束可能不合适。
----------------------------是的，我这样做是为了谋生。



以下为原文

eteam00 wrote:
I am carefully rereading the SelectIO part of the data sheet.
 
Also read UG381, section  beginning on page 70 (version 1.4).
 
The dynamic input delay modes are designed for applications where the phase relationship between sampling clock and individual input data is unknown (or unknowable) because of (variable) skews.  This description applies to HDMI inputs (no specification whatsoever for channel matching), and seems to fit your multi-channel, multi-ADC inputs as well.
 
 Each converter provides its own clock, so all of a converter's outputs are synchronous to its clock. All eight converters are essentially independent. So skew between converters is uninteresting.
 
 
And delaying one signal is easier than delaying eight, which is why I wonder if I can actually do that -- IODELAY2 on the clock input line.
 
Don't  forget the maxim:  the FPGA is already fully bought and paid for -- it costs no more to use 8 delays on 8 input data than 1 delay on the clock.  Using per-channel delay give you per-channel de-skewing, which means additional timing margin.
 
Yep, noted. I'm looking for "easiest." As in, "easiest to understand" and "easiest to get working."
 
 
The ADC clock output is 100 MHz. Dunno if that's "too high."
 
Phhfffft!  Is per-channel data rate 100Mb/sec (SDR) or 200Mb/sec (DDR) ?
 
If you use source-synchronous sampling of input data, you need to group ADC input channels and clocks together into BUFIO regions.  Then you need to reconcile ADC-ADC skews when crossing from multiple input clock domains(s) to single system clock domain.
 
It's 200 Mb/sec DDR, so a 100 MHz clock. My first cut at doing my data capturing and the processing that follows seems to meet timing with plenty of slack.
 
And it appears that the tools just put the clocks on BUFGs so it was nothing fancier than that. But that didn't address the delay issue, although perhaps my constraint wasn't proper.
 
 

 
----------------------------Yes, I do this for a living.

此外，如果转换器供应商提供其设备的总线功能模型，那将是很好的。
我问过。
他们忽略了这个要求。
另一家转换器供应商发给我一个IBIS文件。
这实际上比缺乏回应更烦人。
----------------------------是的，我这样做是为了谋生。



以下为原文

Plus it would be nice if the converter vendor supplied a bus-functional model of their device. I've asked. They ignored the request.
 
Another converter vendor sent me an IBIS file. that was actually more annoying than the lack of response.
----------------------------Yes, I do this for a living.

每个转换器都提供自己的时钟，因此所有转换器的输出都与其时钟同步。
所有八个转换器基本上是独立的
所以转换器之间的偏差是无趣的。
然后，当从多个输入时钟域跨越到单个系统时钟域时，您需要协调ADC-ADC偏移。
有几种方法可以协调ADC之间的偏差。
我要说的是，每通道延迟会在一个膨胀中消除两个问题（数据时钟对齐和clockX clockY对齐）。
我在寻找“最简单的”。
就像“最容易理解”和“最容易上班”一样。
它只会在一开始就疼。
一旦你第一次将大脑包裹起来，就会变得更容易。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Each converter provides its own clock, so all of a converter's outputs are synchronous to its clock. All eight converters are essentially independent. So skew between converters is uninteresting.
 
Then you need to reconcile ADC-ADC skews when crossing from multiple input clock domains(s) to single system clock domain.
 
There are several ways to reconcile the skews between ADCs.  The point I'm making is that the per-channel delay slays both problems (data <-> clock alignment and clockX <-> clockY alignment) in one swell foop.
 
I'm looking for "easiest." As in, "easiest to understand" and "easiest to get working."
 
It only hurts in the beginning.  Once you wrap your brain around it the first time, it gets easier.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

好的......我使用Core Generator的SelectIO接口向导来创建一个整齐地处理我的情况的模板。
忘记了这个系统中有多个ADC的事实。
那不相关。
所以我有一个ADC，它在8条线路上输出一个16位DDR数据总线，以及一个基本上与数据对齐的源同步时钟。
时钟是100 MHz。
该向导创建了以下逻辑：
用于LVDS输入时钟的IBUFGDS_DIFF_OUT
两个IODELAY2，一个用于_p时钟，另一个用于_n时钟。
IDELAY_VALUE设置为0，IDELAY_TYPE设置为FIXED。
校准逻辑被禁用。
这些饲料
两个BUFIO2，DIVIDE = 1，一个用于_p时钟，另一个用于_n时钟。
_p BUFIO2的DIVCLK输出也用作主时钟（在BUFG之后）与所有出来的数据同步。
它还创建了八条数据路径，每条路径都包含：
每个数据输入差分对的IBUFDS，用于馈送
IODELAY2，其IOCLK0和IOCLK1输入由BUFIO2（上面）IOCLK输出驱动。
CLK输入来自上面的主时钟（_p时钟的DIVCLK输出上的BUFIO2），CAL信号来自一些神奇的外部逻辑。
BUSY输出转到外部逻辑。
DATAOUT信号输入
IDDR2用于数据位，IDDR2的C0和C1时钟也是BUFIO2的IOCLK输出。
这合成并放置和路由并满足100 MHz时序约束。
但是有一个停滞不前的问题。
根据UG381第72页，在“校准示例”下，“然而，延迟值的任何更新仅在输入数据流中的四次转换发生后发生。”
我的输入来自ADC。
我无法保证在连接ADC的系统处于空闲状态时，我会在每条输入数据线上看到四个转换。
如果发送端是FPGA或其他可以发送具有足够转换的训练模式的东西，我可以看到这种方案有效。
但这不是我正在处理的事情。
所以校准概念是正确的。
我想我可以选择IODELAY2的“FIXED”IDELAY_TYPE，如果我相信数据表每次点击最大延迟并按照公式（DS162第47页note2），我会得到一个延迟值。
但我读到的一切都说基本上我选择的任何值都是不可靠的。而且模拟模型甚至没有尝试对其进行正确建模。
它允许您设置每次点击延迟值，默认为75 ps，但它似乎不起作用。
所以我回过头来单独延迟时钟输入（仍然通过IODELAY2s运行数据线，延迟为FIXED和0抽头）。
但是如何校准时钟延迟呢？
我可以将BUFIO2输出反馈到时钟的IODELAY2的IOCLK0和IOCLK1输入吗？
感谢您的任何见解。
----------------------------是的，我这样做是为了谋生。



以下为原文

OK ... I used the Core Generator's SelectIO Interface Wizard to create a template which neatly handles my situation. FORGET the fact that there's more than one ADC in this system. That's not relevant.
 
So I have an ADC which outputs a 16-bit DDR data bus on 8 lines, and a source-synchronous clock which is essentially aligned with the data. The clock is 100 MHz.
 
The wizard created the following logic:
 

• IBUFGDS_DIFF_OUT for the LVDS input clock, which feeds
  
• Two IODELAY2s, one for the _p clock and the other for the _n clock. The IDELAY_VALUE is set to 0 and the IDELAY_TYPE is set to FIXED. The calibration logic is tied off as disabled. These feed
  
• Two BUFIO2s, with DIVIDE = 1 and again one for the _p clock and the other for the _n clock. The _p BUFIO2's DIVCLK output is also used as the main clock (after a BUFG) synchronous with all of the data that comes out of this. 
  

It also created eight data paths, each with:

• IBUFDS for each data input differential pair, which feed an
  
• IODELAY2, whose IOCLK0 and IOCLK1 inputs are driven by the BUFIO2s' (above) IOCLK outputs. The CLK input comes from the main clock above (BUFIO2 on the _p clock's DIVCLK output), and the CAL signal comes from some magic external logic. The BUSY output goes to that external logic. The DATAOUT signal feeds the
  
• IDDR2 for the data bit, and the IDDR2s' C0 and C1 clocks are also the BUFIO2s' IOCLK outputs.
  

This synthesizes and places and routes and meets the 100 MHz timing constraint.
 
But there's a showstopping problem. According to UG381 page 72, under "Calibration Example," "However, any update in delay values only takes place after four transitions in the input data stream occur." My inputs come from an ADC. I cannot guarantee that I'll see four transitions on each input data line while the system to which the ADC is connected is idle.
 
I can see this scheme working if the transmit side is an FPGA or something else that can send a training pattern with sufficient transitions. But that's not what I'm dealing with. So the calibration concept is right out.
 
I suppose I can choose the IODELAY2's "FIXED" IDELAY_TYPE, and if I believe the data sheets max delays for each tap and follow the equation (DS162 page 47 note2), I'll get a delay value. But everything I've read says that basically any value I choose is unreliable.  And the simulation model doesn't even attempt to model it properly. It lets you set a delay-per-tap value which defaults to 75 ps, and it didn't seem to work.
 
So I am back to delaying the clock input alone (still running the data lines through IODELAY2s with the delays FIXED and at 0 taps). But how does one calibrate the clock delay? Can I feed the BUFIO2 outputs back into the clock's IODELAY2s' IOCLK0 and IOCLK1 inputs? 
 
Thanks for any insights.
----------------------------Yes, I do this for a living.

None


以下为原文

I'm picking and choosing the bits to which I'm responding, and my wisdom is far from the final word on these questions.  Having offered the requisite weasel words, on to the field of battle...
 
FORGET the fact that there's more than one ADC in this system. That's not relevant.
 
The subject {may | will} likely rear up (again) when the various clock domains meet in the middle.
 
So I have an ADC which outputs a 16-bit DDR data bus on 8 lines, and a source-synchronous clock which is essentially aligned with the data. The clock is 100 MHz.
 
In other words -- more questions:

• Clock edges are (essentially) co-incident with data transitions, yes?
  
• Data rate (per bit or channel) is 200Mb/sec, yes?
  
• Input clock vs. input data skew (from the ADC data sheet) is yet unknown.  How much of the 'perfection' 5nS data valid window -- relative to input clock -- can be reasonably spent on FPGA logic/interconnect skews and setup/hold times?
  
• Because clock is half-rate (DDR), not only is the clock/data skew important, but the clock/data duty cycle is also important.  Clock doubling -- to use SDR rather than DDR clocking -- is off the table with asymmetric clock/data waveforms.
  

 
I tried an experiment (using 13.4), see what you think...
 

• Spartan-6, -2 speed grade
  
• IDELAY2 on both ADC clock input and ADC data inputs (results are better than with IDELAY only on data)
  
• IDELAY2 delay tap values are fixed, no calibration used  - 0 for clock input, 50 for data
  
• clock is buffered with BUFG, not BUFIO2
  

The static timing analyser datasheet report list worst case D=> clk setup as -1.404nS at the package pins
The static timing analyser datasheet report list worst case D=> clk hold as 3.627nS at the package pins
Total data valid width required is ~2.25nS (out of 5nS), roughly centred between ADC clock edges
 
Here are the timing constraints I used:
NET "clk100m" TNM_NET = "clk100m";
TIMESPEC "TS_clk100m" = PERIOD "clk100m" 10.0 ns HIGH 50%;
NET "adc_rx*" OFFSET = IN -1.0 VALID 3.5ns BEFORE "inclk100m" RISING;
NET "adc_rx*" OFFSET = IN -1.0 VALID 3.5ns BEFORE "inclk100m" FALLING;
 
And here is the code:
 
module s6_forum_top (
  input         inclk100m, // 100MHz input clock from ADC
  input  [15:0] adc_rx, // 16-channel input data from ADC, DDR
  output [31:0] adc_dout ); // 32-bit output data, SDR

wire   [31:0]  rxd;
reg    [31:0]  rxd_reg;

(* IOB="TRUE" *)
reg    [31:0]    adc_out; // output register

wire clk100_dly;    // clock delayed

IODELAY2 # ( // ADC input clock delay
    .COUNTER_WRAPAROUND("WRAPAROUND"),
    .DATA_RATE("SDR"),
    .DELAY_SRC("IDATAIN"),
    .IDELAY2_VALUE(0),
    .IDELAY_MODE("NORMAL"),
    .IDELAY_TYPE("FIXED"),
    .IDELAY_VALUE(0),       // # taps for fixed input delay (0-255) Set to 0
    .ODELAY_VALUE(0),
    .SERDES_MODE("NONE"),
    .SIM_TAPDELAY_VALUE(75) // Per tap delay used for simulation in ps
)
clock_dly (
    .BUSY      (),
    .DATAOUT   (),
    .DATAOUT2  (clk100_dly),
    .DOUT      (),
    .TOUT      (),
    .CAL       (1'b0),
    .CE        (1'b0),
    .CLK       (1'b0),
    .IDATAIN   (inclk100m),
    .INC       (1'b0),
    .IOCLK0    (1'b0),
    .IOCLK1    (1'b0),
    .ODATAIN   (),
    .RST       (1'b0),
    .T         (1'b0) );

BUFG BUFG_inst ( // clock buffer
    .O    (clk100m),
    .I    (clk100_dly) );
 
// 16 ADC (DDR) data inputs, 32 de-muxed outputs, using IDELAY2 and IDDR
datadelayreg inbit00 (
 .clock_p    (clk100m),    // DDR clock
 .indata     (adc_rx[0]),  // DDR input data
 .outdata_a  (rxd[0]),     // SDR de-muxed data
 .outdata_b  (rxd[16]) );  // SDR de-muxed data

datadelayreg inbit01 (
 .clock_p    (clk100m),
 .indata     (adc_rx[1]),
 .outdata_a  (rxd[1]),
 .outdata_b  (rxd[17]) );

datadelayreg inbit02 (
 .clock_p    (clk100m),
 .indata     (adc_rx[2]),
 .outdata_a  (rxd[2]),
 .outdata_b  (rxd[18]) );

datadelayreg inbit03 (
 .clock_p    (clk100m),
 .indata     (adc_rx[3]),
 .outdata_a  (rxd[3]),
 .outdata_b  (rxd[19]) );

datadelayreg inbit04 (
 .clock_p    (clk100m),
 .indata     (adc_rx[4]),
 .outdata_a  (rxd[4]),
 .outdata_b  (rxd[20]) );

datadelayreg inbit05 (
 .clock_p    (clk100m),
 .indata     (adc_rx[5]),
 .outdata_a  (rxd[5]),
 .outdata_b  (rxd[21]) );

datadelayreg inbit06 (
 .clock_p    (clk100m),
 .indata     (adc_rx[6]),
 .outdata_a  (rxd[6]),
 .outdata_b  (rxd[22]) );

datadelayreg inbit07 (
 .clock_p    (clk100m),
 .indata     (adc_rx[7]),
 .outdata_a  (rxd[7]),
 .outdata_b  (rxd[23]) );

datadelayreg inbit08 (
 .clock_p    (clk100m),
 .indata     (adc_rx[8]),
 .outdata_a  (rxd[8]),
 .outdata_b  (rxd[24]) );

datadelayreg inbit09 (
 .clock_p    (clk100m),
 .indata     (adc_rx[9]),
 .outdata_a  (rxd[9]),
 .outdata_b  (rxd[25]) );

datadelayreg inbit10 (
 .clock_p    (clk100m),
 .indata     (adc_rx[10]),
 .outdata_a  (rxd[10]),
 .outdata_b  (rxd[26]) );

datadelayreg inbit11 (
 .clock_p    (clk100m),
 .indata     (adc_rx[11]),
 .outdata_a  (rxd[11]),
 .outdata_b  (rxd[27]) );

datadelayreg inbit12 (
 .clock_p    (clk100m),
 .indata     (adc_rx[12]),
 .outdata_a  (rxd[12]),
 .outdata_b  (rxd[28]) );

datadelayreg inbit13 (
 .clock_p    (clk100m),
 .indata     (adc_rx[13]),
 .outdata_a  (rxd[13]),
 .outdata_b  (rxd[29]) );

datadelayreg inbit14 (
 .clock_p    (clk100m),
 .indata     (adc_rx[14]),
 .outdata_a  (rxd[14]),
 .outdata_b  (rxd[30]) );

datadelayreg inbit15 (
 .clock_p    (clk100m),
 .indata     (adc_rx[15]),
 .outdata_a  (rxd[15]),
 .outdata_b  (rxd[31]) );

always @(posedge clk100m) rxd_reg <= rxd; // fabric registers
always @(posedge clk100m) adc_out <= rxd_reg; // IOB output registers

assign adc_dout = adc_out;

endmodule
 
// define datadelayreg module used for data inputs
module datadelayreg (
 input clock_p, indata,
 output outdata_a, outdata_b ) ;
 
 wire delay_data;

 IODELAY2 #(
   .COUNTER_WRAPAROUND("WRAPAROUND"),
   .DATA_RATE("DDR"),                 // "SDR" or "DDR"
   .DELAY_SRC("IDATAIN"),
   .IDELAY2_VALUE(0),
   .IDELAY_MODE("NORMAL"),
   .IDELAY_TYPE("FIXED"),    // "FIXED", "DEFAULT"
   .IDELAY_VALUE(75),  // hand-tweaked value, # taps for fixed input delay (0-255) - Set to 75
   .ODELAY_VALUE(0),
   .SERDES_MODE("NONE"),
   .SIM_TAPDELAY_VALUE(75) ) // Per tap delay used for simulation in ps
  IODELAY2_rxd (
   .BUSY     (),
   .DATAOUT  (delay_data),
   .DATAOUT2 (),
   .DOUT     (),
   .TOUT     (),
   .CAL      (1'b0),
   .CE       (1'b0),
   .CLK      (1'b0),
   .IDATAIN  (indata),
   .INC      (1'b0),
   .IOCLK0   (1'b0),
   .IOCLK1   (1'b0),
   .ODATAIN  (),
   .RST      (1'b0),
   .T        (1'b0) );

  IDDR2 #(.DDR_ALIGNMENT("NONE"),
    .INIT_Q0(1'b0),
    .INIT_Q1(1'b0),
    .SRTYPE("SYNC") )
   rx_adc (
    .C0    ( clock_p),
    .C1    (~clock_p), //BUFG output clock is inverted in IO switchbox
    .CE    (1'b1),
    .D     (delay_data),
    .R     (1'b0),
    .S     (1'b0),
    .Q0    (outdata_a),    // de-muxed ADC input
    .Q1    (outdata_b) );  // de-muxed ADC input

endmodule
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

所以我回过头来单独延迟时钟输入（仍然通过IODELAY2s运行数据线，延迟为FIXED和0抽头）。
但是如何校准时钟延迟呢？
我可以将BUFIO2输出反馈到时钟的IODELAY2的IOCLK0和IOCLK1输入吗？
您没有校准时钟输入IDELAY2块。
如果将时钟输入延迟设置为点击＃0（最小延迟设置），则会因时钟余量而变大，因为时钟输入延迟将更加密切地跟踪数据输入延迟 - 因为数据和时钟都在运行（类似
）IDELAY2块。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

So I am back to delaying the clock input alone (still running the data lines through IODELAY2s with the delays FIXED and at 0 taps). But how does one calibrate the clock delay? Can I feed the BUFIO2 outputs back into the clock's IODELAY2s' IOCLK0 and IOCLK1 inputs?
 
You don't calibrate the clock input IDELAY2 block.  If the clock input delay is set to tap#0 (the minimum delay setting), you win big with timing margins because the clock input delay will much more closely track the data input delay -- because both data and clock are running through (similar) IDELAY2 blocks.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.