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你好,我写了一个简单的代码,由两个计数器组成,从15开始倒计时。两个时钟都按计划运行。
接下来我想在代码中实现DCM,以便将时钟信号相移90度并在32MHz下运行它们。 我已成功将DCM代码实现到现有代码中; 但是当我尝试使用新的输出时钟信号时,我遇到了问题。 我试着将输出时钟直接输入我的计数器代码。 这给出了以下错误:模式in的参数clk0 / clk90无法与正式模式输出端口关联。 我的问题是这个错误是什么意思? 还可以直接将DCM输出时钟实现为我的计数器代码中使用的传统时钟吗? 代码写在ISE 14.5上。 库IEEE;使用IEEE.STD_LOGIC_1164.ALL;使用IEEE.STD_LOGIC_ARITH.ALL;使用IEEE.STD_LOGIC_UNSIGNED.ALL; -------------------------- -------------------------------------------------- -------------------------------------------------- --------------------------------------实体Counter2_DCM isPort(clk:在STD_LOGIC中;重置:在 STD_LOGIC; clk0:在STD_LOGIC中; clk90:在STD_LOGIC中; DIRECtiON0:在STD_LOGIC中; DIRECTION90:在STD_LOGIC中; COUNT_OUT0:out STD_LOGIC_VECTOR(3 downto 0); COUNT_OUT90:out STD_LOGIC_VECTOR(3 downto 0)); end Counter2_DCM; -------------------------------------------------- --------------------------------架构Counter2_DCM的行为是 COMPONENT DCM1 PORT(CLKIN_IN:IN std_logic; RST_IN:IN std_logic; CLKIN_IBUFG_OUT:OUT std_logic; CLK0_OUT:OUT std_logic; CLK2X_OUT:OUT std_logic; CLK90_OUT:OUT std_logic; LOCKED_OUT:OUT std_logic); 结束组成部分; signal count_int0:std_logic_vector(3 downto 0):=“0000”; signal count_int90:std_logic_vector(3 downto 0):=“0000”;信号锁定:std_logic; --------------- -------------------------------------------------- - - - - - - - - -开始 Inst_DCM1:DCM1端口映射(CLKIN_IN => clk,RST_IN =>复位,CLKIN_IBUFG_OUT =>打开,CLK0_OUT => clk0,CLK2X_OUT =>打开,CLK90_OUT => clk90,LOCKED_OUT =>已锁定); -------------------------------------------------- -------------------------------- process(clk0) --ERROR:HDLParsers:1411 - “E:/Taylor/FPGA/DMC_counter/Counter1_DCM.vhd”第48行。模式输入的参数clk0不能与正式的模式输出端口关联。 如果clk0 ='1'并且clk0'event则开始,然后如果DIRECTION0 ='1'则count_int0,否则count_int0结束if; 结束if;结束进程; COUNT_OUT0 ------------------------------------------- --------------------------------------- 过程(clk90) --ERROR:HDLParsers:1411 - “E:/Taylor/FPGA/DMC_counter/Counter1_DCM.vhd”第50行。模式in的参数clk90不能与正式的模式输出端口关联。 如果clk90 ='1'并且clk90'event则开始,然后如果DIRECTION90 ='1'则count_int90否则count_int90结束if; 结束if;结束进程; COUNT_OUT90 ------------------------------------------- -------------------------------------------------- -------------------------------------------------- --------------------- end Behavioral; 以上来自于谷歌翻译 以下为原文 Hello, I've written a simple code consisting of two counters that count down from 15. Both the clocks functioned as planned. I next wanted to implement DCM into the code in order to phase shift the clock signals 90 degrees and run them both at 32MHz. I successfully implemented the DCM code into my existing code; however when I tried to use the new output clock signals I ran into problems. I tried to feed the output clocks directly into my counter code. This gave the following error: Parameter clk0/clk90 of mode in cannot be associated with a formal port of mode out. My questions are what does this error mean? Also is it possible to directly implement the DCM output clocks as a conventional clock as used in my counter code? The code was written on ISE 14.5. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- entity Counter2_DCM is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; clk0 : in STD_LOGIC; clk90 : in STD_LOGIC; DIRECTION0 : in STD_LOGIC; DIRECTION90 : in STD_LOGIC; COUNT_OUT0 : out STD_LOGIC_VECTOR (3 downto 0); COUNT_OUT90 : out STD_LOGIC_VECTOR (3 downto 0)); end Counter2_DCM; ---------------------------------------------------------------------------------- architecture Behavioral of Counter2_DCM is COMPONENT DCM1 PORT( CLKIN_IN : IN std_logic; RST_IN : IN std_logic; CLKIN_IBUFG_OUT : OUT std_logic; CLK0_OUT : OUT std_logic; CLK2X_OUT : OUT std_logic; CLK90_OUT : OUT std_logic; LOCKED_OUT : OUT std_logic ); END COMPONENT; signal count_int0 : std_logic_vector(3 downto 0) := "0000"; signal count_int90 : std_logic_vector(3 downto 0) := "0000"; signal locked : std_logic; ---------------------------------------------------------------------------------- begin Inst_DCM1: DCM1 PORT MAP( CLKIN_IN => clk, RST_IN => reset, CLKIN_IBUFG_OUT => open, CLK0_OUT => clk0, CLK2X_OUT => open, CLK90_OUT => clk90, LOCKED_OUT => locked ); ---------------------------------------------------------------------------------- process (clk0) --ERROR:HDLParsers:1411 - "E:/Taylor/FPGA/DMC_counter/Counter1_DCM.vhd" Line 48. Parameter clk0 of mode in can not be associated with a formal port of mode out. begin if clk0='1' and clk0'event then if DIRECTION0='1' then count_int0 <= count_int0 + 1; else count_int0 <= count_int0 - 1; end if; end if; end process; COUNT_OUT0 <= count_int0; ---------------------------------------------------------------------------------- process (clk90) --ERROR:HDLParsers:1411 - "E:/Taylor/FPGA/DMC_counter/Counter1_DCM.vhd" Line 50. Parameter clk90 of mode in can not be associated with a formal port of mode out. begin if clk90='1' and clk90'event then if DIRECTION90='1' then count_int90 <= count_int90 + 1; else count_int90 <= count_int90 - 1; end if; end if; end process; COUNT_OUT90 <= count_int90; ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- end Behavioral; |
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实体声明将clk0和clk90定义为输入,并且它们连接到DCM1上的输出,这是冲突。
------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 The entity declaration has clk0 and clk90 defined as inputs and these are connected to outputs on the DCM1 this is a conflict. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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