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嗨,
我在使用DCM时遇到了问题。我的要求实际上是将clk信号的频率从50MHz降低到20MHz。在10个时钟脉冲之后,dcm的输出会显示出来。 我使用的是ISE版本12.1。 FPGA系列:Spartan 3E 设备:XC3S250E 包装:CP132 速度:-4 使用的DCM属性: CLK_FEEDBACK = NONE CLKDV_DIVIDE = 2.5 CLKFX_DIVIDE = 5 = CLKFX_MULtiPLY 2 CLKIN_DIVIDE_BY_2 = FALSE CLKIN_PERIOD = 20.000 CLKOUT_PHASE_SHIFT = NONE DESKEW_ADJUST = SOURCE_SYNCHRONOUS DFS_FREQUENCY_MODE = LOW DLL_FREQUENCY_MODE = LOW DUTY_CYCLE_CORRECTION = TRUE FACTORY_JF = 16'hC080 PHASE_SHIFT = 0 STARTUP_WAIT = FALSE 是否有任何设置更改我需要实现以避免输出的延迟。如果不是我想知道,如果任何其他方式我可以实现这个信号。 以上来自于谷歌翻译 以下为原文 Hi, I have an issue in using a DCM.My requirement is actually to cut down the frequency of clk signal from 50MHz to 20 MHz.The output of a dcm is getting displayed after 10 clock pulses. I am using ISE version 12.1. FPGA family:Spartan 3E Device:XC3S250E PAckage:CP132 speed:-4 The DCM attributes used : CLK_FEEDBACK = NONE CLKDV_DIVIDE = 2.5 CLKFX_DIVIDE = 5 CLKFX_MULTIPLY = 2 CLKIN_DIVIDE_BY_2 = FALSE CLKIN_PERIOD = 20.000 CLKOUT_PHASE_SHIFT = NONE DESKEW_ADJUST = SOURCE_SYNCHRONOUS DFS_FREQUENCY_MODE = LOW DLL_FREQUENCY_MODE = LOW DUTY_CYCLE_CORRECTION = TRUE FACTORY_JF = 16'hC080 PHASE_SHIFT = 0 STARTUP_WAIT = FALSE Is there any setting changes i needs to implement to avoid the latency at the output.If not i would like to kno if any other way i can acheive this signal. |
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8个回答
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您无法真正避免延迟,因为DCM需要时间来锁定输入信号。
如果您只想将输入时钟除以2.5,那么您可以使用结构触发器代替 一个DCM。 这种方法的缺点是产生的20 MHz信号不会 相位与输入时钟对齐。 顺便说一句,你的应用程序需要在重置后如此快地运行时钟? - Gabor - Gabor 以上来自于谷歌翻译 以下为原文 You can't really avoid the delay because the DCM needs time to lock to the input signal. If all you want is to divide the input clock by 2.5, then you could use fabric flip-flops instead of a DCM. The down side to this method is that the resulting 20 MHz signal will not be phase aligned with the input clock. By the way, what is your application that needs the clock running so soon after reset? -- Gabor -- Gabor |
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为什么不通过合并现有的重置和DCM锁定状态输出端口来生成另一个重置信号?
这会解决你的整体问题吗? 以上来自于谷歌翻译 以下为原文 Why don't you generate another reset signal by comining your existing reset and the DCM locked status output port? Will that solve your overall problem? |
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嗨Gabor,
谢谢你的回复!!! 实际上,该信号用于为ADC提供时钟.ADC的输入来自传感器设备,该传感器设备仅存在很短的时间。因此我希望ADC能够立即响应以提高系统效率并使用此功能。 DCM用于更好的抖动管理,我认为使用触发器无法在很大程度上避免这种情况。如果我对我所做的观察错误,请告诉我。 以上来自于谷歌翻译 以下为原文 Hi Gabor, Thanks for ur reply!!! Actually the signal is used to clock an ADC.and the input to the ADC is from a sensor device which will be present for only a short duration of time.So i wanted ADC to respond immediately to make the system more efficient and i used this DCM for better jitter management which i guess could not be avoided to a large extend by using flip-flop.Please advice me if i am wrong with the observations i made. |
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Re:DCM问题
11-10-201104:31 PM 为什么不通过合并现有的重置和DCM锁定状态输出端口来生成另一个重置信号? 这会解决你的整体问题吗? 嗨, 如果你能详细描述那将是很棒的。甚至我用复位信号尝试了所有的可能性。延迟发生了。 :smileysad: 以上来自于谷歌翻译 以下为原文 Re: DCM issue 11-10-2011 04:31 PM Why don't you generate another reset signal by comining your existing reset and the DCM locked status output port? Will that solve your overall problem? Hi, It will be greatful if u could elaborate the description.And even I tried all the possibilities with the reset signal.Again the delay is occuring. :smileysad: |
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为什么不通过合并现有的重置和DCM锁定状态输出端口来生成另一个重置信号?
这会解决你的整体问题吗? 嗨, 如果你能详细描述那将是很棒的。甚至我用复位信号尝试了所有的可能性。延迟发生了。 :smileysad: 以上来自于谷歌翻译 以下为原文 Why don't you generate another reset signal by comining your existing reset and the DCM locked status output port? Will that solve your overall problem? Hi, It will be greatful if u could elaborate the description.And even I tried all the possibilities with the reset signal.Again the delay is occuring. :smileysad: |
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deepakprathap写道:
嗨Gabor, 谢谢你的回复!!! 实际上,该信号用于为ADC提供时钟.ADC的输入来自传感器设备,该传感器设备仅存在很短的时间。因此我希望ADC能够立即响应以提高系统效率并使用此功能。 DCM用于更好的抖动管理,我认为使用触发器无法在很大程度上避免这种情况。如果我对我所做的观察错误,请告诉我。 实际上DCM只能添加抖动,而不是清理它。 如果你需要低抖动,你最好使用 PLL,最好不嵌入FPGA中。 请注意,对于单端信号,任何噪声开启 电源轨还会增加抖动。 因此,最好不要在嘈杂的环境中运行时钟 像FPGA一样。 一种解决方案可能是在您的系统中添加一个20 MHz晶体振荡器,由干净的电源供电 过滤后的电源并分别缓冲到FPGA和ADC(缓冲器也应该运行 关于清洁供应)。 如果您决定在FPGA内部创建时钟,则结构分频器将不再具有抖动 DCM(也可能更少),但它的占空比不会接近50%。 如果您说传感器输入仅在短时间内可用,那也让我感到困扰。 请记住,FPGA在上电后可能需要相当长的时间进行配置。 模拟中的时序图显示配置后发生的情况,以及 在许多毫秒的配置时间后,将发生200 ns左右的延迟。 - Gabor - Gabor 以上来自于谷歌翻译 以下为原文 deepakprathap wrote:Actually a DCM can only add jitter, not clean it up. If you need low jitter, you're better off using a PLL, preferably not embeded in the FPGA. Note that for single-ended signals, any noise on the power rails also adds jitter. So you're better off not running the clock through a noisy environment like the FPGA. One solution may be to add a 20 MHz crystal oscillator to your system, powered from a clean filtered supply and buffered separately to the FPGA and the ADC (the buffer should also run on the clean supply). If you decide to create the clock inside the FPGA, the fabric divider will have no more jitter than the DCM (and might have less), but it's duty cycle will not be as close to 50%. It also bothers me that you say that the sensor input is only available for a short period of time. Remember that an FPGA can take a considerable length of time to configure after power on. The timing diagram in your simulation shows what happens after configuration, and the 200 ns or so of added delay will happen after many milliseconds of configuration time. -- Gabor -- Gabor |
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deepakprathap写道:
嗨Gabor, 谢谢你的回复!!! 实际上,该信号用于为ADC提供时钟.ADC的输入来自传感器设备,该传感器设备仅存在很短的时间。因此我希望ADC能够立即响应以提高系统效率并使用此功能。 DCM用于更好的抖动管理,我认为使用触发器无法在很大程度上避免这种情况。如果我对我所做的观察错误,请告诉我。 实际上DCM只能加速,而不是清理它。 如果你需要低抖动,你最好使用 PLL,最好不嵌入FPGA中。 请注意,对于单端信号,任何噪声开启 电源轨还会增加抖动。 因此,最好不要在嘈杂的环境中运行时钟 像FPGA一样。 一种解决方案可能是在您的系统中添加一个20 MHz晶体振荡器,由干净的电源供电 过滤后的电源并分别缓冲到FPGA和ADC(缓冲器也应该运行 关于清洁供应)。 如果您决定在FPGA内部创建时钟,则结构分频器将不再具有抖动 DCM(也可能更少),但它的占空比不会接近50%。 如果您说传感器输入仅在短时间内可用,那也让我感到困扰。 请记住,FPGA在上电后可能需要相当长的时间进行配置。 模拟中的时序图显示配置后发生的情况,以及 在许多毫秒的配置时间后,将发生200 ns左右的延迟。 - Gabor 这个我最初想要在FPGA套件上实现。该套件本身有一个内置时钟发生器,可产生50Mhz信号。问题是信号被采集并处理到20MHz,以作为ADC的输入。 外部IC.DCM只是一个在此频率上运行的模块,还有其他模块在50MHz上运行。 所以我想在这个时间点无法实现包含外部时钟振荡器的选项。所以我可以尝试使用你建议的其他选项。 以上来自于谷歌翻译 以下为原文 deepakprathap wrote:Actually a DCM can only add jitter, not clean it up. If you need low jitter, you're better off using a PLL, preferably not embeded in the FPGA. Note that for single-ended signals, any noise on the power rails also adds jitter. So you're better off not running the clock through a noisy environment like the FPGA. One solution may be to add a 20 MHz crystal oscillator to your system, powered from a clean filtered supply and buffered separately to the FPGA and the ADC (the buffer should also run on the clean supply). If you decide to create the clock inside the FPGA, the fabric divider will have no more jitter than the DCM (and might have less), but it's duty cycle will not be as close to 50%. It also bothers me that you say that the sensor input is only available for a short period of time. Remember that an FPGA can take a considerable length of time to configure after power on. The timing diagram in your simulation shows what happens after configuration, and the 200 ns or so of added delay will happen after many milliseconds of configuration time. -- Gabor This one i would like to implement on a FPGA kit initially.The kit itself has got an inbuilt clock generator which generates a 50Mhz signal.The issue is that the signal is taken and processed to 20MHz for making as input to the ADC which is an external IC.And the DCM is just one module that operates on this freq and there are also other modules which operates on 50MHz. So i guess the option of including an external clock oscillator could not be implemented at this point of time.So may be i try with the other option u have suggested. |
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我不喜欢使用DCM为ADC计时的声音。
我曾在我的职业生涯早期试图做到这一点,我的65 MSPS ADC非常困惑,无法在7 MHz以上的频率下可靠地锁定我的DCM生产时钟(尽管这可能与无关的信号完整性问题相结合)。 然后,我查看了频谱分析仪上的DCM输出,非常惊骇。 我的投票是使用外部低抖动振荡器(它们不是太昂贵),或者如果您需要频率捷变或与其他时钟相位对齐,则使用PLL或DDS(但您总是可以使用DCM来转换ADC的低抖动) 对于其他FPGA逻辑,20 MHz时钟到50 MHz)。 以上来自于谷歌翻译 以下为原文 I don't like the sound of clocking an ADC using a DCM. I tried to do this once earlier in my career and my 65 MSPS ADC got very confused and couldn't reliably lock to my DCM-produced clock at frequencies above 7 MHz (though this was probably compounded by unrelated signal integrity issues). I then had a look at the DCM output on a spectrum analyser and was pretty horrified. My vote goes to using an external, low jitter oscillator (they're not too expensive), or a PLL or DDS if you require frequency agility or phase alignment with other clocks (but you could always use the DCM to convert the ADC's low jitter 20 MHz clock to 50 MHz for your other FPGA logic). |
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