如何锁定DCM

DCM在开机时不会被锁定，因此您的分配将导致它永远不会从重置中释放。
使用状态机检测失锁，在适当的时间内置位复位，然后暂停一段时间以使DCM有时间获取锁定。



以下为原文

The DCM will not be locked at power on, so your assignment will cause it to never be released from reset.
 
Use a state machine to detect loss of lock, assert reset for the appropriate amount of time, then hold off for a while to give the DCM time to acquire the lock.

谢谢
使用状态机检测失锁，断言重置
适当的时间，然后暂缓一段时间给DCM
获得锁定的时间。
我用过
总是@（posedge CLKFX）开始lock_shift如果（lock_shift == 4'b1111）开始lock_real
高电平有效RST引脚必须连接到动态信号或必须接地。
RST输入必须置位三个有效CLKIN周期或更长时间。
因此有必要将RESET作为外部输入（接地），我是否正确？
如何使用RESET for DCM和其余逻辑？
任何帮助，将不胜感激？
问候
费萨尔



以下为原文

Thanks
 
Use a state machine to detect loss of lock, assert reset for the appropriate amount of time, then hold off for a while to give the DCM time to acquire the lock.
 
I have used as
 
always@(posedge CLKFX)
begin
    lock_shift <= {lock_shift[2:0], LOCKED};
        if(lock_shift == 4'b1111)
                begin
                lock_real <= 1'b1; // DCM stable
                end
        else
                begin
                lock_real <= 1'b0; // Unstable
                end
end
 
 
In this i did not use  any external RESET . What I did is
 
rst_reg=1'b0;
assign RESET = rst_reg;
 
Did I miss anything ?
 
From the datasheet
 
If the DCM loses lock—i.e., the LOCKED output was High then goes Low—then the FPGA
application must assert RST to force the DCM to reacquire the input clock frequency.

The active-High RST pin either must connect to a dynamic signal or must be
tied to ground. The RST input must be asserted for three valid CLKIN cycles or longer.
 
 
So it is necessary to have a RESET as external input (ground) , Am I correct ?
 
How to use the RESET for DCM and rest of the logic ?
 
Any help would be appreciated?
 
Regards
 
Faisal
 
 

我认为断言RESET输入会导致时钟输出停止，并导致LOCK输出被置低。
如果您依靠PLL或DCM时钟输出来同步清除RESET信号，则可能需要等待很长时间。
我对正确使用RESET输入到PLL或DCM的理解是： 
当LOCK因CLOCK输入中断或干扰而丢失时，在输入CLOCK重新建立并稳定后，短暂置位RESET以复位内部LOCK电路。
这将加速重新获取LOCK到新的输入时钟。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

I believe that asserting RESET input causes clock outputs to halt, and causes LOCK output to be de-asserted.
If you are relying on PLL or DCM clock outputs to synchronously clear the RESET signal, you might be waiting a very long time.
 
My understanding of the proper use of RESET input to PLL or DCM is:

when LOCK has been lost due to CLOCK input interruption or disturbance, assert RESET briefly to reset the internal LOCK circuitry after the input CLOCK has been re-established and stabilised.  This will speed up re-acquisition of LOCK to the new input clock.

- Bob Elkind
SIGNATURE:
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Summary:
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pfaisalbe写道：
因此有必要将RESET作为外部输入（接地），我是否正确？
在那段代码中，您根本没有重置DCM。
手册说你必须将RST连接到动态控制信号（状态机或其他东西）或接地（如果你不想打扰它，也许你的输入时钟非常稳定）。
只要输入时钟良好，您的代码就可以正常工作。
也许其他人可以评论是否依赖任何DCM永远锁定是一个好主意？
我想它不是。
DS162规定，LOCK_DLL是DCM获取锁定所需的最长时间，为5 ms，因此您的逻辑必须至少在重置之间暂停一段时间，否则它有可能无法锁定。



以下为原文

 

pfaisalbe wrote:
[size=11.8056px] 
So it is necessary to have a RESET as external input (ground) , Am I correct ?
 

In that piece of code, you didn't reset the DCM at all. The manual says you have to connect RST to a dynamic control signal (a state machine, or something else) OR ground (if you don't want to bother with resetting it, perhaps if your input clock is very stable). Your code should work, as long as your input clock is good. Maybe someone else can comment on whether it's a good idea to ever rely on any DCM remaining locked forever? I imagine it's not.
 
DS162 states that LOCK_DLL, the maximum time that the DCM can take to acquire a lock, is 5 ms, so your logic must pause for at least this amount of time between resets or else there's a chance it won't ever lock.

谢谢Bob，
当LOCK由于CLOCK输入中断或干扰而丢失时，
短暂置位RESET以在之后复位内部LOCK电路
输入CLOCK已重新建立并稳定下来。
这会加快
重新获取LOCK到新的输入时钟。
Undestood。
如何获得DCM的RESET输入并重置逻辑？
亲切的问候
费萨尔



以下为原文

Thanks Bob,
 
when LOCK has been lost due to CLOCK input interruption or disturbance, assert RESET briefly to reset the internal LOCK circuitry after the input CLOCK has been re-established and stabilised.  This will speed up re-acquisition of LOCK to the new input clock.
 
 
Undestood. How to get a  RESET input  to DCM and reset of the logic ?
 
 
Kind Regards
 
Faisal

pfaisalbe写道：
Undestood。
如何获得DCM的RESET输入并重置逻辑？
在伪代码中：
如果未锁定，DCM重置= 1
等三个周期
DCM重置= 0
等待5毫秒
去开始吧
除了永久重置DCM之外，您可能还想做一些更智能的事情，比如向用户发送错误消息。



以下为原文

 

pfaisalbe wrote:
[size=11.8056px] 
Undestood. How to get a  RESET input  to DCM and reset of the logic ?[size=11.8056px] 

 
In pseudo-code:
 
If not locked, DCM reset = 1
Wait three cycles
DCM reset = 0
Wait 5 ms
Go to start
 
You might want to do something more intelligent in addition to resetting the DCM forever, like sending an error message to the user.

joelby写道：
pfaisalbe写道：
Undestood。
如何获得DCM的RESET输入并重置逻辑？
在伪代码中：
如果未锁定，DCM重置= 1
等三个周期
DCM重置= 0
等待5毫秒
去开始吧
除了永久重置DCM之外，您可能还想做一些更智能的事情，比如向用户发送错误消息。
除非你的意思是“在锁定的下降边缘”而不是“如果DCM未锁定”，那么这将无效。 
LOCK时需要延迟以防止锁定（双关语意）
不活跃。
我的典型状态机包括一个长计数器（可能是16位）
当LOCK处于活动状态时保持复位（DCM锁定时保持为零）。
这个计数器是时钟
通过输入DCM的输入时钟或其他一些恒定时钟。
你不能
使用DCM输出为复位电路提供时钟，因为它们在复位期间不运行。
然后，当计数器接近其最大计数时，我断言重置为DCM。
重要：
必须允许计数器在达到最大计数时回绕到零。
这是怎么回事
重置被释放。
只有当DCM在延迟时间内锁定时，整个电路才有效，否则就是你
得到连续的重置。
这就是柜台很大的原因。
它也过滤掉瞬间
落入LOCK输出。
另一点：除了LOCK输出，DCM还有一些STATUS输出，
这也可以表明输入信号的丢失。
LOCK不一定会无效
如果DCM的输入时钟突然停止，因为LOCK信号本身很明显
在DCM内部计时。
所以我通常使用状态位（我忘了哪些，但是
它应该从用户指南中的描述以及LOCKED中显而易见
发出信号以检测DCM是否正常运行。
伪代码：
在其他一些时钟： 
如果LOCKED和STATUS == Normal，则COUNTER = 0 
否则COUNTER = COUNTER + 1（带包装） 
DCM重置=（COUNTER> MAX_COUNT-N）
在这种情况下，当使用DCM自己的输入时钟时，N可以小到
4为3周期最小复位脉冲。
使用其他频率时可能需要
变得更大
只要MAX_COUNT  -  N，通常不会使N变大
为DCM提供足够的时间来锁定。
Phewww ...
-  Gabor
-  Gabor



以下为原文

 

joelby wrote:
 

pfaisalbe wrote:
[size=11.8056px] 
Undestood. How to get a  RESET input  to DCM and reset of the logic ?[size=11.8056px] 

 
In pseudo-code:
 
If not locked, DCM reset = 1
Wait three cycles
DCM reset = 0
Wait 5 ms
Go to start
 
You might want to do something more intelligent in addition to resetting the DCM forever, like sending an error message to the user.

 
That won't work either unless you mean "On falling edge of Locked" rather than "If DCM not Locked.
  You need a delay to prevent a lock-up (pun intended) when LOCK
is not active.  My typical state machine includes a long counter (maybe 16 bits) that is
held reset when LOCK is active (stays zero while DCM is locked).  This counter is clocked
either by the input clock that feeds the DCM or by some other constant clock.  You cannot
use DCM outputs to clock the reset circuitry as they do not run during reset.
 
Then I assert reset to the DCM when the counter is near its max count.  IMPORTANT:
the counter must be allowed to wrap back to zero when it reaches max count.  This is how
the reset is released.
 
The whole circuit works only if the DCM locks within the delay time, otherwise you
get continuous resets.  That's why the counter is large.  It also filters out momentary
drops in the LOCK output.
 
Another point:  In addition to the LOCK output, the DCM has some STATUS outputs,
which can also indicate loss of input signal.  LOCK will not necessarily go inactive
if the DCM's input clock stops abruptly since the LOCK signal itself is apparently
clocked inside the DCM.  So I usually use the status bits (I forget which ones, but
it should be obvious from the descriptions in the Users Guide) as well as the LOCKED
signal to detect whether the DCM is running properly.
 
Pseudo-code:
 
On some other clock:
  If LOCKED and STATUS == Normal then COUNTER = 0
  Else COUNTER = COUNTER + 1 (with wrap)
  DCM Reset = (COUNTER > MAX_COUNT-N)
 
In this case when using the DCM's own input clock then N could be as small as
4 for a 3 cycle minimum reset pulse.  When using another frequency it may need
to be larger.  It generally doesn't hurt to make N larger as long as MAX_COUNT - N
gives enough time for the DCM to lock.
 
Phewww...
 
-- Gabor
-- Gabor

以下为原文

 

qd0090，
你是新来的。
我们的主持人为这些论坛建立了一套规则，你可以在这里阅读。
第一：请不要向现有主题发布不相关的主题或问题。
开始一个新的线程，这样两个对话可以保持清晰和简洁。
第二：请不要在多个主题中发布相同的主题或问题。
这称为交叉发布。
将讨论保持在一个线程中，这样可以更容易地进行讨论并更容易参与讨论。
如果您使用的是Virtex系列产品，请在Virtex论坛的新主题中重新发布。
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感谢您尊重这些规则。
我在您的交叉发布条目中添加了相同的回复。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

qd0090,
 
You are new here.  Our hosts have established a set of rules for these forums, you can read them here.
 
First:  Please do not post a unrelated topic or question to an existing thread.   Start a new thread, so the two conversations can remain distinct and concise.
 
Second:  Please do not post the same topic or question in multiple threads.  This is called cross-posting.  Keep the discussion in one thread, which makes it easier to follow the discussion and makes it easier to participate in the discussion.
 
If you are using a Virtex family part, please re-post in a new thread in the Virtex forum.
If you are using a Spartan family part, please re-post in a new thread in the Spartan forum.
 
Thank you for respecting the rules.  I have placed the same response in your cross-posted entry.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

IBUFG必须介于输入板和所有负载之间，包括DCM。
所以
你的原理图应该在连接点之前向上和向左移动。
-  Gabor



以下为原文

The IBUFG must go between the input pad and all loads, including the DCM.  So in
your schematic it should move up and to the left before the conenction dot.
-- Gabor