SLR分配的Vivado放置错误

你好@ prasath_a。
可重复的opt_design可以附加吗？
这可以帮助确定问题。
或者，使用完整零件值，可以创建测试用例。
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-----------------------不要忘记回答，kudo，并接受为解决方案.-------------
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以下为原文

Hi @prasath_a. Is the reproducible post-opt_design available to attach? This could help identify the problem. Alternatively, with the full part value, a test case could be created.  
 
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标记，
我有完整的项目，大小约38 MB。
无法上传。
还有其他方式可以分享吗？
Prasath



以下为原文

Mark,
 
I have the complete project and the size comes around 38 MB. Unable to upload it. Is there any other way to share?
 
Prasath

该设计似乎打算使用直接的Laguna TX  - > Laguna RX连接。
这在Vivado中可以从2018.1版本开始，但目前需要对连接的两侧都有LOC和bel约束。
以下是一个例子。
与RX相比，TX侧的Y坐标将偏移120。
set_property BEL TX_REG0 [get_cells u_pkt_pt_blk / slr0_wr_data_ff_reg [0]] set_property LOC LAGUNA_X6Y240 [get_cells u_pkt_pt_blk / slr0_wr_data_ff_reg [0]]
set_property BEL RX_REG0 [get_cells u_pkt_pt_blk / slr0_wr_data_ff_1_reg [0]] set_property LOC LAGUNA_X6Y120 [get_cells u_pkt_pt_blk / slr0_wr_data_ff_1_reg [0]]
此外，应该使用基于时钟区域的pblock。
原始错误与仅包含Laguna网站的pblock有关。
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-----------------------不要忘记回答，kudo，并接受为解决方案.-------------
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以下为原文

The design looks to be intending to use a direct Laguna TX -> Laguna RX connection. This is possible in Vivado starting with the 2018.1 version, but currently requires both a LOC and bel constraint for both sides of the connection. Below is an example. The Y coordinates for the TX side will be offset by 120 compared with the RX.
 
set_property BEL TX_REG0 [get_cells u_pkt_pt_blk/slr0_wr_data_ff_reg[0]]
set_property LOC LAGUNA_X6Y240 [get_cells u_pkt_pt_blk/slr0_wr_data_ff_reg[0]]

set_property BEL RX_REG0 [get_cells u_pkt_pt_blk/slr0_wr_data_ff_1_reg[0]]
set_property LOC LAGUNA_X6Y120 [get_cells u_pkt_pt_blk/slr0_wr_data_ff_1_reg[0]]
 
Also, a clock region based pblock should be used. The original errors were related to the pblock containing only Laguna sites.
 
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Don’t forget to reply, kudo, and accept as solution.
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