执行Vivado2017.1设计项目时出错

@shubhamn，
不，您只需要查看时钟引脚的新IO端口连接，这些连接现在已锁定到具有时钟功能的引脚。
既然你提到你是Vivado的新手，我强烈建议你参加在线培训。
https://www.xilinx.com/training.html
以下是我用作GCIO引脚以克服位置错误的新位置约束：
set_property PACKAGE_PIN AK47 [get_ports mii_rtl_tx_clk]
set_property PACKAGE_PIN AL49 [get_ports mii_rtl_rx_clk]
--Syed
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在原帖中查看解决方案



以下为原文

@shubhamn,
 
No, You only need to Check out the new IO ports connections of clock pin which are now locked to the Clock capable pin.
Since you mentioned you are new to Vivado, I would strongly recommend you to take the online training. 
https://www.xilinx.com/training.html
 
The following are the new location constraints which I used as GCIO pins to overcome the place error:
set_property PACKAGE_PIN AK47 [get_ports mii_rtl_tx_clk]
set_property PACKAGE_PIN AL49 [get_ports mii_rtl_rx_clk]
 
--Syed
 
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@shubhamn，
检查以下AR：
https://www.xilinx.com/support/answers/66659.html
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
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-------------------



以下为原文

@shubhamn,

Check the below AR:
https://www.xilinx.com/support/answers/66659.html
 
--Syed
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@shubhamn，
上述答复记录是否有帮助？
如果您仍然面临同样的错误，请分享post opt dcp文件，该文件位于/.runs/impl_1/***_opt.dcp
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
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-------------------



以下为原文

@shubhamn,
 
Did the above Answer record helped? If you still face the same error the please share the post opt dcp file which will be located in /.runs/impl_1/***_opt.dcp
 
--Syed
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嗨syedz，
我在STEP1之后按照上面的命令出现以下错误： -
[放置30-675]支持全局时钟的IO引脚和BUFG对的次优放置。如果此子设计可接受此子优化条件，则可以使用.xdc文件中的CLOCK_DEDICATED_ROUTE约束将此消息降级为
警告。
但是，强烈建议不要使用此覆盖。
这些示例可以直接在.xdc文件中使用，以覆盖此时钟规则。
design_1_i / axi_ethernetlite_0 / U0 / NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST / IBUFCTRL_INST（IBUFCTRL.O）被锁定到IOB_X0Y223（在SLR 0）design_1_i / axi_ethernetlite_0 / U0 / NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.CLOCK_BUFG_RX（BUFGCE.I）被临时放置由clockplacer上BUFGCE_X0Y96
（在SLR 0中）上述错误可能与其他连接的实例有关。
以下是所有相关时钟规则及其各自实例的列表。
时钟规则：rule_bufgce_bufg_conflict状态：PASS规则描述：一对中只有一个可用站点中的一个（BUFGCE或BUFGCE_DIV / BUFGCTRL）可以同时使用design_1_i / axi_ethernetlite_0 / U0 / NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.CLOCK_BUFG_RX（BUFGCE.O）
由clockplacer临时放置在BUFGCE_X0Y96上（在SLR 0中）
所以在此之后我搜索了IOB_X0Y223和BUFGCE_X0Y96以检查那里的CLOCK区域，我发现时钟区域（X0Y4）是相同的。
那我为什么会得到同样的错误。
我还附上了下面的design_1_wrapper_opt.dcp文件。
design_1_wrapper_opt.dcp 2413 KB



以下为原文

Hi syedz,
I followed above commands after STEP1 I got below error :-
 
[Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/axi_ethernetlite_0/U0/NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST/O] >

    design_1_i/axi_ethernetlite_0/U0/NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X0Y223 (in SLR 0)
    design_1_i/axi_ethernetlite_0/U0/NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.CLOCK_BUFG_RX (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y96 (in SLR 0)

    The above error could possibly be related to other connected instances. Following is a list of
    all the related clock rules and their respective instances.

    Clock Rule: rule_bufgce_bufg_conflict
    Status: PASS
    Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
    used at the same time
    design_1_i/axi_ethernetlite_0/U0/NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.CLOCK_BUFG_RX (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y96 (in SLR 0)
 
 
So after this I searched for IOB_X0Y223 and BUFGCE_X0Y96 to check there CLOCK region and I found that there clock regions(X0Y4) are same. Then why I am getting the same error.
 
I have also attached the design_1_wrapper_opt.dcp file below.
 
            design_1_wrapper_opt.dcp ‏2413 KB

@shubhamn，
感谢分享post opt dcp。
我能够在我的机器上重现相同的错误。
该错误是由于toclock端口被锁定到非GCIO引脚。
您需要将此端口更改为支持时钟的引脚，或者如果端口无法更改，则使用以下约束。
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i / axi_ethernetlite_0 / U0 / NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST / O]
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
--------------------------------------------------
-------------------



以下为原文

@shubhamn,
 
Thanks for sharing the post opt dcp. I was able to reproduce the same error on my machine. 
The error is due to clock port is locked to a non-GCIO pin. 

 
You will need to change this port to a clock capable pin or use the below constraint if the port cannot be changed.
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/axi_ethernetlite_0/U0/NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST/O]
 
--Syed
---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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@shubhamn，
我看到“design_1_i / axi_ethernetlite_0 / U0 / NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST / IBUFCTRL_INST”其他一些时钟端口也放在非GCIO引脚中。
请检查附带的xdc文件，该文件提供了传递位置。
问候，赛义德
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
--------------------------------------------------
-------------------
test.xdc 24 KB



以下为原文

@shubhamn,
 
I see along with "design_1_i/axi_ethernetlite_0/U0/NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST/IBUFCTRL_INST" some other clock ports are also placed in non-GCIO pin. Please check the attached xdc file which gives passing placement.
 
Regards,
Syed
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---------------------------------------------------------------------------------------------            test.xdc ‏24 KB

@syedz
所以，您是否希望我将.xdc文件替换为您附加的文件？
你能解释我的设计中的问题吗？
我是使用Vivado的新手。



以下为原文

@syedz
 
So do you want me to replace my .xdc file with the one you have attached?
 
Can you please explain basically what is the problem in my design?
I am new to using Vivado.
 

@shubhamn，
不，您只需要查看时钟引脚的新IO端口连接，这些连接现在已锁定到具有时钟功能的引脚。
既然你提到你是Vivado的新手，我强烈建议你参加在线培训。
https://www.xilinx.com/training.html
以下是我用作GCIO引脚以克服位置错误的新位置约束：
set_property PACKAGE_PIN AK47 [get_ports mii_rtl_tx_clk]
set_property PACKAGE_PIN AL49 [get_ports mii_rtl_rx_clk]
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
--------------------------------------------------
-------------------



以下为原文

@shubhamn,
 
No, You only need to Check out the new IO ports connections of clock pin which are now locked to the Clock capable pin.
Since you mentioned you are new to Vivado, I would strongly recommend you to take the online training. 
https://www.xilinx.com/training.html
 
The following are the new location constraints which I used as GCIO pins to overcome the place error:
set_property PACKAGE_PIN AK47 [get_ports mii_rtl_tx_clk]
set_property PACKAGE_PIN AL49 [get_ports mii_rtl_rx_clk]
 
--Syed
 
---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
---------------------------------------------------------------------------------------------

@syedz
由于这个原因，我的所有错误都得到了解决。
但现在我收到了一些警告
1. [filemgmt 20-644]找到循环参考：'/ axi_ethernetlite_v3_0_10 / axi_interface / rtl'[“/ home / shubhamn / test_2017.1 / test_2017.1.srcs / sourcess_1 / bd / design_1 /ipshared / 83a1 / hdl / xsi-ethernetlite_v3_0_vh_rfs
.vhd“：0]  -  >>'/ axi_ethernetlite_v3_0_10 / axi_interface / rtl'[”/ home/shubhamn/test_2017.1/test_2017.1.srcs/sources_1/bd/design_1/ipshared/83a1/hdl/axi_ethernetlite_v3_0_vh_rfs.vhd
“：12303]
2. [电源33-332]发现切换活动意味着高扇出复位网络被断言超过一段时间，这可能导致功率分析不准确。解决方案：要查看并修复问题，请在GUI中运行Power Constraints Advisor
工具> Power Constraints Advisor或使用-advisory选项运行report_power以生成文本报告。
3. [DRC CFGBVS-1]缺少CFGBVS和CONFIG_VOLTAGE设计属性：current_design中未设置CFGBVS和CONFIG_VOLTAGE电压属性。
配置组电压选择（CFGBVS）必须设置为VCCO或GND，并且CONFIG_VOLTAGE必须设置为正确的配置电压，以确定支持0的引脚的I / O电压。建议指定这些
使用GUI中的“编辑设备属性”功能或使用以下语法直接在XDC文件中：set_property CFGBVS value1 [current_design] #where value1是VCCO或GNDset_property CONFIG_VOLTAGE value2 [current_design] #where value2是提供给配置的电压
bank 0有关详细信息，请参阅设备配置用户指南。



以下为原文

@syedz
 
All of my errors are resolved thanks for that.
 
But now I am getting some warnings like
 
1. [filemgmt 20-644] Circular Reference Found: '/axi_ethernetlite_v3_0_10/axi_interface/rtl' ["/home/shubhamn/test_2017.1/test_2017.1.srcs/sources_1/bd/design_1/ipshared/83a1/hdl/axi_ethernetlite_v3_0_vh_rfs.vhd":0] -->> '/axi_ethernetlite_v3_0_10/axi_interface/rtl' ["/home/shubhamn/test_2017.1/test_2017.1.srcs/sources_1/bd/design_1/ipshared/83a1/hdl/axi_ethernetlite_v3_0_vh_rfs.vhd":12303]
2. [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
3. [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.

@shubhamn
请为此查询创建一个新线程。
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
--------------------------------------------------
-------------------



以下为原文

@shubhamn
 
Please create a new thread for this query.
 
--Syed
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