放置错误BUFG实例位于下半部SLR

你好@ pumaju1808
set_property LOC BUFG_location [get_cells BUFG_instance_name]
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以下为原文

Hi @pumaju1808
 
set_property LOC BUFG_location [get_cells BUFG_instance_name]
Thanks,
Deepika.
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你好@ pumaju1808
我认为一个接一个地限制BUFG是向前发展的方式。
但我建议你分析BUFG负载以及关于BUFG到特定位置的约束。
谢谢，
维奈
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以下为原文

Hi @pumaju1808
 
I think constraining one by one BUFG is the way to move forward.
But I suggest you to analyze the BUFG loads and with respect to that constraint BUFG to specific locations.
 
Thanks,
Vinay
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打开opt_design.dcp并找到（Ctrl + F）设计中的所有BUFG。然后使用xdc约束开始定位所需的BUFG并运行place_design.you可以在TCL控制台中运行以下命令opt_designplace_ports这会在内存中留下部分位置。
然后，您可以在SLR0的下半部分查看所有实例占用BUFG站点的内容。
即使您在BUFG实例上没有LOC约束，很可能在与BUFG关联的单元格上应用了LOC约束。
例如，如果IO端口正在驱动BUFG并且IO端口被锁定到IO组或时钟区域，则相关联的BUFG需要放置在限制BUFG放置的同一组中。
谢谢和RegardsBalkrishan -----------------------------------------------
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以下为原文

open opt_design.dcp and find (Ctrl+F) all the BUFGs in the design.

Then start LOCing the required BUFGs using xdc constraints and run place_design.

you can run below commands in TCL console



opt_design

place_ports



This leaves partial placement in memory. You can then see what all instances are occupying BUFG sites in lower half of SLR0. Even though you dont have LOC constraints on BUFG instances, it is quite possible that you have LOC constraints applied on the cells associated with BUFG. For example if IO port is driving BUFG and the IO port is locked to a IO bank or clock region then the associated BUFG needs to be placed in the same bank which restricts the BUFG placement.




Thanks and Regards
Balkrishan
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你好@ pumaju1808
我希望你使用7系列SSI设备。
当设计具有超过16个BUFG时，您需要遵循一些额外的时钟指南。
尝试减少设计中的BUFG（看看你是否可以使用BUFR和BUFH），请参阅第111-112页，网址为：http：//www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug949-vivado-design-methodology.pdf
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi @pumaju1808
 
I hope you are using 7 series SSI device. There are some additional clocking guidelines you need to follow when design has more than 16 BUFG's.
 
Try reducing the BUFG's in your design (see if you can use BUFR and BUFH), refer to page-111,112 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug949-vivado-design-methodology.pdf 
Thanks,
Deepika.
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谢谢你的回复，
任何人都可以给我一个具体的例子如何约束一个BUFG？
如何“使用xdc约束定位所需的BUFG”？
谢谢



以下为原文

Thanks for your responses,
 
Can anyone give me a specific example how it would be constraint a BUFG? How do I  "LOCing the required BUFGs using xdc constraints"  ?
 
Thanks

你好@ pumaju1808
set_property LOC BUFG_location [get_cells BUFG_instance_name]
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi @pumaju1808
 
set_property LOC BUFG_location [get_cells BUFG_instance_name]
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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