Vivado 16.2放置错误（30-512）

嗨，
我正在开发一个已经从ISE升级到vivado的项目。
我们有一个块diaram，其中使用axi_ethernet_interface与程序框图进行通信，它完美地工作，直到我们升级到Vivado 16.2。
由于某种原因升级后，它无法进行放置并给我这个错误。
错误：[放置30-512]时钟区域分配失败。
时钟缓冲器 'microblaze_i / axi_ethernet_0 / U0 / eth_mac / U0 / tri_mode_ethernet_mac_i / gmii_interface / bufio_gmii_rx_clk'（BUFIO）在CLOCKREGION_X0Y3放置在现场BUFIO_X0Y12。
其负载需要放置在时钟区域CLOCKREGION_X0Y3和CLOCKREGION_X0Y3所包围的区域中。
它的一个负载的“microblaze_i / axi_ethernet_0 / U0 / eth_mac / U0 / tri_mode_ethernet_mac_i / gmii_interface / rx_er_to_mac_reg”（埃塞俄比亚联邦民主共和国）被放置在现场ILOGIC_X1Y149在CLOCKREGION_X1Y2这是允许的area.Resolution外：请确保时钟缓冲器载荷放置在其
可达时钟区域。
在之前的设计中，我们没有它抱怨的这个IOBUF，现在在新设计中它出于某种原因放置了这个IOBUF。
这可能是由于微生物或以太网核心的更新，因为该项目是在几年前完成的，我们需要将其升级到我们拥有的最新工具和固件。
我附上了3张图片：
1.以前的设计
2. FDRE被放在一个切片中，我猜vivado正在抱怨这个FDRE。
3. FDRE的另一张图片清楚地表明了这一点。
请在这方面帮助我。
谢谢，
阿米尔·侯赛因



以下为原文

Hi,

I am working on a project which has been upgraded to vivado from ISE. We have a block diaram in which are using axi_ethernet_interface to communicate with the block diagram and it was working perfectly until we upgraded to Vivado 16.2.

After the upgrade for some reason it is not able to do the placement and gives me this error.

ERROR: [Place 30-512] Clock region assignment has failed. Clock buffer 'microblaze_i/axi_ethernet_0/U0/eth_mac/U0/tri_mode_ethernet_mac_i/gmii_interface/bufio_gmii_rx_clk' (BUFIO) is placed at site BUFIO_X0Y12 in CLOCKREGION_X0Y3. Its loads need to be placed in the area enclosed by clock regions CLOCKREGION_X0Y3 and CLOCKREGION_X0Y3. One of its loads 'microblaze_i/axi_ethernet_0/U0/eth_mac/U0/tri_mode_ethernet_mac_i/gmii_interface/rx_er_to_mac_reg' (FDRE) is placed in site ILOGIC_X1Y149 in CLOCKREGION_X1Y2 which is outside the permissible area.
Resolution: Please ensure that clock buffer loads are placed within its reachable clock regions.

In the previous design we were not having this IOBUF which it complains about and now in the new design it places this IOBUF for some reason. It might be due to the update of the microblaze or the ethernet core because the project was done some years ago and we need to upgrade it to the latest tools and firmware we have.

I have attached 3 pictures:

1. Previous design

2. FDRE which it been placed in a slice and i guess vivado is complaining about this FDRE.

3. Another picture for the FDRE to make things clear.

Kindly help me in this regard.

Thanks,

Aamir Hussain