放置过程中收到了很多错误信息

@moshed
你为什么使用设备？
DSP级联有一些规则/限制。
查看您正在使用的设备的DSP用户指南。
来自7系列DSP用户指南：https：//www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf
对于SSI设备，DSP切片不能跨插入器级联（SLR边界） 
路径中级联的最大数量仅受芯片中一列中DSP48E1片的总数限制。
--Syed
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在原帖中查看解决方案



以下为原文

@moshed
 
Why device are you using? There are some rules/restrictions with DSP cascading. check out the DSP user guide of the device you are using. 
From 7 series DSP user guide: https://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf 
For SSI device, the DSP slices cannot be cascaded across the interposer (SLR boundary) 
The maximum number of cascades in a path is limited only by the total number of DSP48E1 slices in one column in the chip. 
 
--Syed
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@moshed
你能分享vivado.log或实现runme.log吗？
我相信这是用户pblock或内部工具生成的pblock，它限制DSP单元放置在打包区域内。
这些级联DSP单元？
如果您可以分享post optpthen，我们可以查看设计。
另请查看以下论坛讨论：
https://forums.xilinx.com/t5/Implementation/ERROR-Place-30-365-The-following-URAM288-macros-could-not-be/td-p/754045
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
--------------------------------------------------
-------------------



以下为原文

@moshed
 
Can you share the vivado.log or implementation runme.log ? 
 
I believe this is either a user pblock or internal tool generated pblock which restricts the DSP cells to be placed within the packed region. Are these cascaded DSP cells? 
 
If you can share the post opt dcp then we can look into the design. Also check the following forum discussion: 
https://forums.xilinx.com/t5/Implementation/ERROR-Place-30-365-The-following-URAM288-macros-could-not-be/td-p/754045
 
--Syed
---------------------------------------------------------------------------------------------
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谢谢Syed。
问题似乎确实是级联的。
当删除级联时，它通过。
但是，我不明白我在级联中做错了什么，
通过将每个偶数DSP模块的RTL pcout连接到下一个奇数DSP模块，设计调用64 DSP并在每对之间级联，例如：
DSP [0] .pcin ='0
DSP [1] .pcout = DSP [0] .pcout
DSP [2] .pcin ='0
DSP [3] .pcout = DSP [2] .pcout
等到63：
DSP [62] .pcin ='0
DSP [63] .pcout = DSP [62] .pcout
这是一种错误的方法吗？
谢谢，
摩西



以下为原文

Thank you Syed.
 
The problem seems to be indeed the cascading.
 
when remove cascade it pass.
However, I don't understand what I'm doing wrong in the cascading,
The design call to 64 DSP and cascade between each pair by connecting in RTL pcout of every even DSP module to the next odd DSP module, for example:
DSP[0].pcin = '0
DSP[1].pcout = DSP[0].pcout
 
DSP[2].pcin = '0
DSP[3].pcout = DSP[2].pcout
 
and so on till 63:
DSP[62].pcin = '0
DSP[63].pcout = DSP[62].pcout
 
Is that a wrong way to do it?
Thanks,
Moshe
 
 
 

@moshed
你为什么使用设备？
DSP级联有一些规则/限制。
查看您正在使用的设备的DSP用户指南。
来自7系列DSP用户指南：https：//www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf
对于SSI设备，DSP切片不能跨插入器级联（SLR边界） 
路径中级联的最大数量仅受芯片中一列中DSP48E1片的总数限制。
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
--------------------------------------------------
-------------------



以下为原文

@moshed
 
Why device are you using? There are some rules/restrictions with DSP cascading. check out the DSP user guide of the device you are using. 
From 7 series DSP user guide: https://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf 
For SSI device, the DSP slices cannot be cascaded across the interposer (SLR boundary) 
The maximum number of cascades in a path is limited only by the total number of DSP48E1 slices in one column in the chip. 
 
--Syed
---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
---------------------------------------------------------------------------------------------

谢谢，这是有帮助的。



以下为原文

Thanks, that's help.