完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
嘿,我有一个警告PAR 468,我以前没见过。
有谁知道该怎么办? 警告说建议会帮助我,但我看不到任何建议。 系统简介:一个模拟数字转换器读出系统,包含一个48 MHz至100 MHz的转换器时钟内核,两个8位宽度的256字节深度块内存和一些其他没有任何规范的子模块...... 提前致谢... 以上来自于谷歌翻译 以下为原文 Hey I'm having a warning PAR 468 that I didnot see before. Does anyone know what to do with this? Also warning says suggestions will assist me but I can't see any suggestion. System in brief: an analog digital converter readout system, containing a 48 MHz to 100 MHzconverter clock core, two 8bit width 256 byte depth block ram and some other submodule without any specification ... Thanks in advance... |
|
相关推荐
3个回答
|
|
macellan85,
你能发布完整的PAR:468消息吗? 您要定位的设备的部件号是多少? 您使用的工具版本是什么? 谢谢, 山姆 不要忘记回复,kudo,并接受解决方案.Xilinx视频设计中心 以上来自于谷歌翻译 以下为原文 macellan85, Can you post the full PAR:468 message? What is the part number of the device that you are targeting? What is the tool version that you are using? Thank you, Sam Don't forget to reply, kudo, and accept as solution. Xilinx Video Design Hub |
|
|
|
嘿@ samk
这是警告标签上的唯一消息: 警告:参数:468 - 您的设计不符合时间要求。 以下是一些帮助您满足设计时间的建议。 我还附上了完整的控制台消息 设备是AES220B斯巴达3AN板 XC3S400AN / ftg256 /速度等级-5 我在Ubuntu 16.04上使用ISE 14.7 谢谢 Console.txt 48 KB 以上来自于谷歌翻译 以下为原文 Hey @samk This is the only message on warning tab: WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design. Also I' ve attached the complete console messages Device is AES220B spartan 3AN board XC3S400AN / ftg256 / speed grade -5 I' m using ISE 14.7 on Ubuntu 16.04 Thank you Console.txt 48 KB |
|
|
|
@ macellan85
我看到PAR的建议:468位于控制台输出中。 使用Timing Analyzer查看时序报告(在ISE中选择“Post-Place& Route Static Timing Report”)。 转到失败的约束并评估每个约束的失败路径。尝试设计目标和时间性能策略(在ISE中选择项目 - >设计目标和策略)以确保在工具中设置最佳选项 时序收敛。使用Xilinx“SmartXplorer”脚本尝试已知的特殊选项组合,以产生非常好的结果。访问Xilinx技术支持网站http://support.xilinx.com并转到“疑难解答 - >技术提示 - >时间和约束“或”TechXclusives->时间关闭“,以获得满足设计时间的提示和建议。未应用的时间约束数量:约束前面的1个星号(*)表示未满足。 这可能是由于设置或保留违规造成的。 时间报告是关闭时间的好资源。 它应该有助于强调项目失败的原因。 萨姆 不要忘记回复,kudo,并接受解决方案.Xilinx视频设计中心 以上来自于谷歌翻译 以下为原文 @macellan85 I see the suggestions for PAR:468 are located in the console output. Review the timing report using Timing Analyzer (In ISE select "Post-Place & Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint. Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options are set in the tools for timing closure. Use the Xilinx "SmartXplorer" script to try special combinations of options known to produce very good results. Visit the Xilinx technical support web at http://support.xilinx.com and go to either "Troubleshoot->Tech Tips->Timing & Constraints" or " TechXclusives->Timing Closure" for tips and suggestions for meeting timing in your design. Number of Timing Constraints that were not applied: 1 Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. The timing report is a good resource for closing timing. It should help highlight the reason that the project is failing timing. -Sam Don't forget to reply, kudo, and accept as solution. Xilinx Video Design Hub |
|
|
|
只有小组成员才能发言,加入小组>>
2420 浏览 7 评论
2823 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2294 浏览 9 评论
3374 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2461 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
1169浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
585浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
451浏览 1评论
2005浏览 0评论
729浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-12-23 13:37 , Processed in 1.450498 second(s), Total 50, Slave 44 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号