请问什么是最大PAR选项？

PAR是否用我上面提到的选项排除了所有可能的路线，或者我可以添加其他选项，
我不确定你是什么意思。
你是说“还有其他选择可能成功吗？”
如果是，那么是的，有。
您可以考虑多通道布局布线和其他实施策略。
话虽这么说，你使用的选项永远不会“失败” -  -xe c意味着“永不停止” - 所以如果它不能满足时间，它将永远运行。
如果你问这个选项是否会“耗尽所有可能的路由解决方案”（即尝试所有可能的布局和路由组合），那么绝对不会。
很容易证明解决方案空间的“详尽”搜索（即使对于相对较小的FPGA）需要比宇宙存在的时间更长的计算时间（通过很多！）。
但你的部分信息没有意义......你说失败是在DDR内存信号中 - 你的意思是“在DDR控制器中的信号”或实际的内存信号（从FPGA出来）本身。
如果是后者，那么这些的通过/失败完全由约束决定，因为这些是（或至少绝对应该）使用IOB触发器，其定时不受放置或布线的影响。
如果它们位于存储器控制器（即MIG）中，那么由于FPGA实现的放置和/或“混乱”性质，您会看到正常的时序故障。
Avrum
在原帖中查看解决方案



以下为原文

Did the PAR exhaust every possible route with the options I stated above or are there other options I can add,
 
I'm not sure what you mean. Are you saying "are there other options that might success where this has failed"? If so, then yes, there are. You can consider Multi-pass place and route, and other implementation strategies. That being said, the options you used will never "fail" - the -xe c means "never stop" - so if it cannot meet timing it will run forever.
 
If you are asking if this option will "exhaust all possible routing solutions" (i.e. try all possible combinations of placement and routing), then absolutely not. It is very easy to prove that an "exhaustive" search of the solution space (even for a relatively small FPGA) takes more compute time than the time the universe has existed (by a LOT!).
 
But a parts of you message don't make sense... You say the failures are in DDR memory signals - do you mean "on signals in the DDR controller" or the actual memory signals (going out of the FPGA) themselves. If it is the latter, then the pass/fail of these are determined purely by the constraints, since these are (or at least absolutely should be) using the IOB flip-flops, whose timing are not impacted by placement or routing. If they are in the memory controller (i.e. the MIG) then you are seeing normal timing failures due to placement and/or the "chaotic" nature of FPGA implementation.
 
Avrum
 
 
View solution in original post

@游泳队
您面临的问题究竟是什么？
当你说带有约束的设计不起作用时，是否有任何警告？
您可以参考以下链接，第9章，第123页：
https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/devref.pdf
问候
罗希特
RegardsRohit -------------------------------------------------
---------------------------------------------请注意 - 请注明
答案为“接受为解决方案”，如果提供的信息是有帮助的。给予您认为有用并回复导向的帖子。感谢K--
--------------------------------------------------
----------------------



以下为原文

@swimteam
 
What exactly  the issue you are facing? When you say design with constraints doesn't work, are there any warnings?
You can refer below link, Chapter 9, page 123 onwards:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/devref.pdf
 
Regards
Rohit
 
 
Regards
Rohit
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ISE PAR完成，但我们的脚本文件会检查错误。
据报道，有些DDR内存信号无法满足时序要求。
如果我删除一些代码，那么时间就满足了。
此代码与DDR无关。
这就是为什么我问这个问题：PAR是否用我上面提到的选项耗尽了所有可能的路线，或者我可以添加其他选项，添加的代码相当小（10或20行）。



以下为原文

The ISE PAR completes, but our script files do checks for errors. It reports that there are some DDR memory signals that are not meeting timing. If I remove some code then the timing is met . This code has nothing to do with the DDR. That's why I asked the question: Did the PAR exhaust every possible route with the options I stated above or are there other options I can add, The code added is rather small (10 or 20 lines).

PAR是否用我上面提到的选项排除了所有可能的路线，或者我可以添加其他选项，
我不确定你是什么意思。
你是说“还有其他选择可能成功吗？”
如果是，那么是的，有。
您可以考虑多通道布局布线和其他实施策略。
话虽这么说，你使用的选项永远不会“失败” -  -xe c意味着“永不停止” - 所以如果它不能满足时间，它将永远运行。
如果你问这个选项是否会“耗尽所有可能的路由解决方案”（即尝试所有可能的布局和路由组合），那么绝对不会。
很容易证明解决方案空间的“详尽”搜索（即使对于相对较小的FPGA）需要比宇宙存在的时间更长的计算时间（通过很多！）。
但你的部分信息没有意义......你说失败是在DDR内存信号中 - 你的意思是“在DDR控制器中的信号”或实际的内存信号（从FPGA出来）本身。
如果是后者，那么这些的通过/失败完全由约束决定，因为这些是（或至少绝对应该）使用IOB触发器，其定时不受放置或布线的影响。
如果它们位于存储器控制器（即MIG）中，那么由于FPGA实现的放置和/或“混乱”性质，您会看到正常的时序故障。
Avrum



以下为原文

Did the PAR exhaust every possible route with the options I stated above or are there other options I can add,
 
I'm not sure what you mean. Are you saying "are there other options that might success where this has failed"? If so, then yes, there are. You can consider Multi-pass place and route, and other implementation strategies. That being said, the options you used will never "fail" - the -xe c means "never stop" - so if it cannot meet timing it will run forever.
 
If you are asking if this option will "exhaust all possible routing solutions" (i.e. try all possible combinations of placement and routing), then absolutely not. It is very easy to prove that an "exhaustive" search of the solution space (even for a relatively small FPGA) takes more compute time than the time the universe has existed (by a LOT!).
 
But a parts of you message don't make sense... You say the failures are in DDR memory signals - do you mean "on signals in the DDR controller" or the actual memory signals (going out of the FPGA) themselves. If it is the latter, then the pass/fail of these are determined purely by the constraints, since these are (or at least absolutely should be) using the IOB flip-flops, whose timing are not impacted by placement or routing. If they are in the memory controller (i.e. the MIG) then you are seeing normal timing failures due to placement and/or the "chaotic" nature of FPGA implementation.
 
Avrum