ISE12.3 PAR不完全但LUT使用率仅为38％（Virtex6器件）

答案很简单：您的设计太慢，无法满足您的时序限制 - 无论是否只使用38％的LUT都无关紧要。
解决方案：
要么放松你的时间限制，要么
优化您的设计。
不可能给你任何具体的建议，但这里有一些指示：
FPGA培训视频
XST用户指南
设计优化白皮书
阿德里安
请在询问之前先查询您的问题。如果有人回答您的问题，请在“接受为解决方案”标记该帖子。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的星）。



以下为原文

The answer is simple: your design is too slow to meet your timing constraints – it doesn't matter whether only 38% of LUTs are used. Solutions:

• Either relax your timing constraints, or
  
• optimize your design.
  

It is impossible to give you any specific advice, but here are some pointers:

• FPGA training videos
  
• the XST user guide
  
• Design Optimization White Papers
  

 
Adrian

Please google your question before asking it.
If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).

嗨，
谢谢回复。
你对这些消息有什么评论，因为PAR遇到Phase4消息，我觉得这条路线会失败。
设置得分为零，但Hold得分非常大，这个消息很奇怪。
ISE句柄可以保持时间问题以增加路径之间的延迟吗？
阶段4：396544未布线;
（设置：0，保持：2195490，组件切换限制：0）实时：12分钟24秒中级状态：2110未布线;
实时：42分钟18秒中级状态：1553未布线;
实时：1小时12分17秒中级状态：1387未布线;
实时：1小时42分18秒中级状态：1275未布线;
实时：2小时12分18秒中级状态：1177未布线;
实时：2小时42分钟21秒中级状态：1056未布线;
实时：3小时12分21秒中级状态：1091未布线;
实时：3小时42分22秒中级状态：964未布线;
实时：4小时12分23秒中级状态：922未布线;
实时：4小时42分25秒警告：路线：464  - 路由器检测到非常密集，拥挤的设计。
路由器极不可能完成设计并满足您的时序要求。
为防止运行时间过长，路由器将改变策略。
路由器现在将完全路由此设计但不改善时序。
此行为将允许您使用静态时序报告和FPGA编辑器来隔离具有时序问题的路径。
这种行为的原因要么是过于困难的约束，要么是在关键时序路径中实现或合成逻辑的问题。
如果您愿意接受长时间运行，请设置选项“-xe c”以覆盖当前行为。
中级状态：692未布线;
实时：5小时42分7秒中级状态：404未布线;
实时：6小时12分8秒中级状态：282未布线;
实时：6小时42分8秒
最好的问候
·乔维



以下为原文

Hi,
Thanks response.
Do you have any comment for these message, because the PAR meet Phase4 message, I feel this route will be failure.
Setup score is zero, but Hold score is very large , this message is very strange.
Can the ISE handle hold time issue to add delay between path?
 
Phase  4  : 396544 unrouted; (Setup:0, Hold:2195490, Component Switching Limit:0)     REAL time: 12 mins 24 secs
  Intermediate status: 2110 unrouted;       REAL time: 42 mins 18 secs

  Intermediate status: 1553 unrouted;       REAL time: 1 hrs 12 mins 17 secs

  Intermediate status: 1387 unrouted;       REAL time: 1 hrs 42 mins 18 secs

  Intermediate status: 1275 unrouted;       REAL time: 2 hrs 12 mins 18 secs

  Intermediate status: 1177 unrouted;       REAL time: 2 hrs 42 mins 21 secs

  Intermediate status: 1056 unrouted;       REAL time: 3 hrs 12 mins 21 secs

  Intermediate status: 1091 unrouted;       REAL time: 3 hrs 42 mins 22 secs

  Intermediate status: 964 unrouted;       REAL time: 4 hrs 12 mins 23 secs

  Intermediate status: 922 unrouted;       REAL time: 4 hrs 42 mins 25 secs

WARNING:Route:464 - The router has detected a very dense, congested design. It is extremely unlikely the router will be able to finish the
   design and meet your timing requirements. To prevent excessive run time the router will change strategy. The router will now work to
   completely route this design but not to improve timing. This behavior will allow you to use the Static Timing Report and FPGA Editor to
   isolate the paths with timing problems. The cause of this behavior is either overly difficult constraints, or issues with the
   implementation or synthesis of logic in the critical timing path. If you are willing to accept a long run time, set the option "-xe c" to
   override the present behavior.
  Intermediate status: 692 unrouted;       REAL time: 5 hrs 42 mins 7 secs

  Intermediate status: 404 unrouted;       REAL time: 6 hrs 12 mins 8 secs

  Intermediate status: 282 unrouted;       REAL time: 6 hrs 42 mins 8 secs
 
Best Regard
Jovi

哪个Virtex-6设备？
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

Which Virtex-6 device?
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

请注意，Route：464警告说：“路由器现在可以完全路由此设计，但不能改善时间”。
路由器正在努力修复这种不可路由设计上的保持时间错误。
在关注时间之前，您需要首先解决拥塞问题。
- 使用和不使用拥塞减少选项“-cr”尝试SmartXplorer
- 检查FPGA编辑器中的部分路由设计，以查看拥塞（未布线网络）的位置
- 同样在FPGA编辑器中，将列表窗口设置为“all nets”，按扇出排序。
选择最高扇出网并查看它们是否与拥挤区域相对应。
- 尝试为拥挤区域减少布局，布局规划或重组设计。
- 如果所有其他方法都失败了，请打开网络案例。
我们在布局器中提供了一些实验算法选项来处理V6拥塞。



以下为原文

Note that the Route:464 warning says: "The router will now work to completely route this design but not to improve timing". The router is making no effort to fix your hold time errors on this unroutable design. You need to address the congestion issues first before focusing on timing.
 
- Try SmartXplorer with and without the congestion reduction option "-cr" 
- Examine the partially routed design in FPGA Editor to see where the congestion (unrouted nets) is
- Also in FPGA Editor, set the list window to "all nets", sort by fanout. Select the highest fanout nets and see if they correspond to the areas of congestion.
- Try some fanout reduction, floorplanning or restructuring of the design for the congested areas.
- If all else fails, open a web case. We have some experimental algorithmic options available in the placer to deal with V6 congestion.