我的BRAM在哪里？

你好@ mauererm
您可以使用ARhttp：//www.xilinx.com/support/answers/58616.html中描述的技术来查找修剪的原因。
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以下为原文

Hi @mauererm
 
You can use the technique described in AR http://www.xilinx.com/support/answers/58616.html to find the reason for the trimming. 
Thanks,
Deepika.
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你好@ mauererm
您是否在设计中正确连接了IP？
看起来实现工具正在修剪BRAM实例。
请打开已实现的设计，然后转到编辑 - >查找并搜索设计中是否有BRAM类型的单元格。
如果结果为空，则打开合成设计并检查BRAM输入和输出是否在原理图中正确连接。
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以下为原文

Hi @mauererm
 
Did you connect the IP properly in the design? It looks like implementation tool is trimming the BRAM instances.
 
Please open implemented design and go to Edit -->find and search if there are any cells of type BRAM in the design. If the results are empty then open synthesized design and check if the BRAM inputs and outputs are connected properly or not in schematic.
 
 
Thanks,
Deepika.
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嗯，实施设计中没有BRAM，但原理图看起来不错;
它就在那里并且有线......



以下为原文

Hmm, no BRAM in implemented design, but schematic looks good; it's all there and wired...

你好@ mauererm
您可以使用ARhttp：//www.xilinx.com/support/answers/58616.html中描述的技术来查找修剪的原因。
谢谢，迪皮卡.----------------------------------------------
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张贴。
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以下为原文

Hi @mauererm
 
You can use the technique described in AR http://www.xilinx.com/support/answers/58616.html to find the reason for the trimming. 
Thanks,
Deepika.
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块存储器生成器提供具有核心生成的示例设计
您可以右键单击并打开示例设计和实现。
检查资源，看看是否能找到差异。
原因可能在于你的设计优化了我的工具。
检查实施阶段的警告你能不能分享你的XCI文件。对于这个配置核心暂时使用32个BRAM你也可以查看资源指南https://www.xilinx.com/support/documentation/ip_documentation/ru/blk
-MEM-gen.html
谢谢和RegardsBalkrishan -----------------------------------------------
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以下为原文

Block Memory Generator provide example design with core generation. You can right click and open example design and implement . Check the resources and see if you can find the difference.

The reason could be here your design got optimize my the tool . check the warnings at implementation stage   

Can you please share you XCI file as well

For this configuration core tentatively use 32 BRAMs

You can also check the resource guide here

https://www.xilinx.com/support/documentation/ip_documentation/ru/blk-mem-gen.html

Thanks and Regards
Balkrishan
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这不仅仅是BRAM，你在实现过程中也会丢失100个DSP片。
这表明设计的很大一部分正在被移除或优化。
在实施过程中查看警告 - 您应该看到大量关于它修剪未连接信号或将引脚连接到常量值的信号。



以下为原文

It's not just BRAM, you're losing something like 100 DSP slices during implementation too. This suggests that a very large part of the design is being removed or optimised away. Have a look through the warnings during implementation - you should see a huge number of ones about it trimming unconnected signals, or connecting pins to constant values.
 
 
 

唉，找到了;
它离下游很远...... :-)谢谢！
一切都好了:-)



以下为原文

Argh, found it; it was pretty far downstream... :-) Thanks! All OK now :-)