怎么从VHDL更新Microblaze BRAM

请检查您是否遵循此操作，然后您可以在自定义IP中将其用作RTL中的单独BRAM。
http://www.xilinx.com/support/answers/52063.html



以下为原文

Please check if you are following this and then you can use this in the custom ip as separate BRAMs in your RTL.
http://www.xilinx.com/support/answers/52063.html

我确实按照您附加的应用笔记进行内存分配。
这一切似乎都很好。
分配给VHDL代码共享的64kb内存位于Microblaze端的地址0x00010000。
我的问题是VHDL方面BRAM中第一个位置的地址是什么？
我相信它是0x00000000，而我的一些同事认为它是0x00010000（即Microblaze方面的相同地址）。
BB



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I am indeed doing the memory allocation per the app note that you attached.  That all seems to work fine.  The 64kb memory allocated to be shared with VHDL code is at address 0x00010000 on the Microblaze side.  My question is what is the address of the first location in the BRAM on the VHDL side?  I believe it to be 0x00000000 while some of my colleagues believe that it is 0x00010000 (i.e., the same address on the Microblaze side).
 
bb

一种解决方案是将您的IP（自定义逻辑）作为AXI主机，可以在总线上启动AXI读取。
因此，它可以访问与Microblaze相同的地址空间。
在这种情况下，BRAM起始地址将为0x00010000。
要了解如何创建自定义AXI母版，您可以参考以下AR：http：//www.xilinx.com/support/answers/37425.htm



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One solution is to make your IP (custom logic) as an AXI master which can initiate AXI reads on the bus. Thus, it can access the same address space as Microblaze does. In that case the BRAM starting address will be 0x00010000.

To learn how to create the custom AXI master, you can refer to the following AR:
http://www.xilinx.com/support/answers/37425.htm

是的，它与microblaze side.0x00010000上的地址相同



以下为原文

Yes It is the same address on microblaze side. 0x00010000

好。
但这似乎是错误的。
它是本地内存总线控制器，为MicroBlaze侧的BRAM提供地址范围。
由于VHDL端没有LMB，我原本预计BRAM的VHDL端将从0x00000000开始。
这是否意味着当您在XPS中配置BRAM并指定其设置具有相同属性的另一个端口的地址范围时？
这可能会阻止MicroBlaze成为32位数据，而您可能希望BRAM的VHDL端是16位数据吗？
第二个问题：你是否必须在VHDL端做一些特殊的事情来访问整个64kb的BRAM？
地址总线是否输出了完整的32位？
由于64kb实际上是多个BRAM，你需要做任何特殊的逻辑来选择正确的BRAM吗？
谢谢你如此敏感。
我可能会再问几个问题。
BB



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OK.  But that seems wrong.  It's the local memory bus controller that supplies the address range for the BRAM on the MicroBlaze side.  Since there is not LMB on the VHDL side, I would have expected that the VHDL side of the BRAM would begin at 0x00000000.
 
Does that mean that when you configure a BRAM in XPS and specify the address range that it sets the other port with the same attributes?  Doesn't this prevent the MicroBlaze from being 32 bit data while you might want the VHDL side of the BRAM to be 16 bit data?
 
A secondary question:  Do you have to do anything special on the VHDL side to access the the entire 64kb of BRAM?  Is the address bus exported a full 32 bits?  Since the 64kb is actually multiple BRAMs, do you need to do any special logic to select the correct BRAM?
 
Thanks for being so responsive.  I'll probably have a few more questions.
 
bb

看看下面的讨论，唯一的区别是他们在谈论DDR而你需要BRAMhttp：//forums.xilinx.com/t5/Embedded-Processor-System-Design/How-to-access-DDR-memory
-with-定制IP-使用-AXI总线/ TD-p / 197412 /高亮/真



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Take a look at the discussion below, the only difference is that they are talking about DDR while you need BRAM

http://forums.xilinx.com/t5/Embedded-Processor-System-Design/How-to-access-DDR-memory-with-Custom-IP-using-AXI-bus/td-p/197412/highlight/true

正确的方法将用于CIP并创建您的RTL接口。
如果您不使用CIP，请参阅上述AR。
很多查询会自动得到解决。
你是怎么写RTL的？



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The correct way would be use to the CIP and create your RTL to interface. If you are not using CIP, Please refer the above ARs. Lot of queries will automatically get resolved. How are you writing the RTL?
 

不确定为什么CIP适用。
CIP创建一个与AXI，PLB或FSL接口的外设。
在此设计中，BRAM通过LMB连接。
自定义VHDL代码位于BRAM的第二个端口上。
我已经根据Xilinx turtorial输出了信号，但是它显示了如何将VHDL连接到设计。
BB



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Not sure why CIP is applicable.  CIP creates a peripheral that interfaces to either AXI, PLB or FSL.  In this design the BRAM is connect via the LMB.  The custom VHDL code is on the second port of the BRAM.  I have exported the signals per a Xilinx turtorial, but it stops short showing how to connect the VHDL to the design.
 
bb

LMB不支持自定义IP。
检查此AR。
http://www.xilinx.com/support/answers/24362.htm



以下为原文

Custom IP is not supported on LMB. Check this AR.
http://www.xilinx.com/support/answers/24362.htm

我明白那个。
VHDL代码不直接连接到Microblaze。
BRAM的一个端口连接到BRAM的PORTA，并且位于本地存储器总线上。
VHDL逻辑需要连接到BRAM的PORTB。
VHDL将与ADC通信，并简单地将模拟值存储在BRAM中。
VHDL与Microblaze总线没有（不应该）任何连接。
谢谢，
BB



以下为原文

I understand that.  The VHDL code does not directly connect to the Microblaze.  One port of the BRAM is connected to PORTA of a BRAM and is on the local memory bus.  The VHDL logic needs to be connected to PORTB of the BRAM.  The VHDL will communicate with an ADC and simply store analog values in the BRAM.  There isn't (shouldn't be) any connection of the VHDL to the Microblaze bus.
 
Thank you,
bb

billbracken写道：
我有一个带有64kb BRAM的Microblaze，带有指令和数据空间（一个端口上的标准I和另一个端口上的D）。
我有另一个64kb只在一个端口上连接到Microblaze并且只包含数据。
第二个端口将由自定义VHDL代码写入。
第二个BRAM地址在Microblaze上为0x00010000。
在导出BRAM的第二个端口以供自定义VHDL代码使用之后，我对VHDL端的BRAM地址感到有些困惑。
BRAM的第一个位置是VHDL侧0x00000000吗？
还是0x00010000？
在我看来，VHDL方面不知道如何在MicroBlaze端配置BRAM。
我也意识到（至少我认为是这种情况）是64kb BRAM是几个物理BRAM。
本地内存总线控制器似乎通过将内存请求映射到正确的BRAM来处理这个问题。
但是，VHDL方面并不清楚（我怀疑它不是这样）。
您是否必须在VHDL端处理单个物理BRAM。
提前致谢，
BB
几年前，当我还在做MicroBlaze时，我基本上做了你想要做的事情：使用传感器接口在一侧写入的双端口BRAM，MicroBlaze可以从另一侧读取（和写入）。
我推出了自己的“IP核”，其中包括与PLB的BRAM连接以及传感器接口。
我记得我必须告诉XPS BRAM的大小，以便MicroBlaze可以与之交谈。
----------------------------是的，我这样做是为了谋生。



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billbracken wrote:
I have a Microblaze with 64kb BRAM with instruction and data space (standard I on one port and D on the other port).  I have another 64kb that is only connected to the Microblaze on one port and will only contain data.  The second port will be written to by custom VHDL code.  The second BRAM address is at 0x00010000 on the Microblaze.  After exporting the second port of the BRAM to be used by the custom VHDL code, I'm a bit confused as to the address of the BRAM on the VHDL side.  Is the first location of the BRAM on the VHDL side 0x00000000?  or is it 0x00010000?  It seems to me that the VHDL side doesn't know about how the BRAM is configured on the MicroBlaze side.  I also realize (at least I think this is the case) is that the 64kb BRAM is actaully several physical BRAMs.  The local memory bus controller seems to take care of this by mapping memory requests to the correct BRAM.  However, it's not clear how (and I suspect that it isn't) on the VHDL side.  Do you have to deal with individual physical BRAMs on the VHDL side.
 
Thanks in advance,
bb

A bunch of years ago, when I still did MicroBlaze, I did basically what you want to do: used dualport BRAMs which a sensor interface wrote to on one side and the MicroBlaze could read (and write) from the other side.
 
I rolled my own "IP core," which included the BRAM connection to the PLB as well as to the sensor interface. I remember I had to tell XPS the size of the BRAM so the MicroBlaze could talk to it.
----------------------------Yes, I do this for a living.

我想我们在同一页上。
基本上没有一个“巫师”去做我想做的事情。
我已经导出了BRAM的第二个端口，使得信号应该可用于VHDL模块。
关于如何将VHDL与Microblaze结合成单个合成实体存在混淆。
我没有VHDL经验，但在Verilog中完成了几个FPGA项目。
第二个问题：Microblaze侧的BRAM与本地内存总线控制器连接。
LMB使用PORTA指定Microblaze总线上BRAM的地址。
地址说是0x00010000。
大小为64kb。
从VHDL的角度来看，PORTB上BRAM的第一个字节的地址是什么/我的论点是它应该是0x00000000，假定一个32位地址。
第三个问题：看起来LMB本质上是“组合”了几个物理BRAM，在Microblaze上制作了一个64kb的块。
似乎在VHDL方面，任何一个都需要一些类似于Microblaze侧的LMB逻辑的逻辑......或者必须单独处理VHDL侧的每个物理BRAM。
我的理解是否正确。
提前致谢。
希望我用正确的语言措辞问题，我想要完成的是明确的。
BB



以下为原文

I think we are on the same page.  Basically there isn't a "wizard" to do what I'd like to do.  I have exported the second port of the BRAM such that the signals should be available  to the VHDL modue.  There is confusion regarding how to tie the VHDL together with the Microblaze into a single synthesized entity.  I have no VHDL experience but have done several FPGA projects in Verilog.
 
A secondary question:  The BRAM on the Microblaze side is connected with an local memory bus controller.  The LMB specifies the address of the BRAM on the Microblaze bus using PORTA.  The address say is 0x00010000.  The size is 64kb.  What is the address of the 1st byte of the BRAM on PORTB from the VHDL perspective/  My contention is that it should be 0x00000000, assuming a 32 bit address.
 
A third question:  It seems like the LMB is in essence "combining" several physical BRAMs to make a 64kb block on the Microblaze.  It seems like on the VHDL side that either one would need some logic similar to the LMB logic on the Microblaze side... or would have to treat each physical BRAM on the VHDL side individually.  Is my understanding correct.
 
Thanks in advance.  Hopefully I have worded the questions using the right language and what I'm trying to accomplish is clear.
 
bb