BUFIO结构锁定导致的放置错误

错误：位置：1073  -  Placer无法为组件创建RPM [BUFIO_RPMs]
axi_adc_4c_0 / axi_adc_4c_0 / USER_LOGIC_I / i_adc_4c / i_adc_if / i_clk_gbuf类型
BUFIO的原因如下。
这个问题的原因：
与此结构相关的一些逻辑被锁定。
这应该导致
要锁定的其余逻辑。
我们应该找到一个问题
BUFIO
axi_adc_4c_0 / axi_adc_4c_0 / USER_LOGIC_I / i_adc_4c / i_adc_if / i_clk_gbuf关闭
芯片边缘以满足相对布局要求
这个逻辑。
以下组件是此结构的一部分：
错误：包装：1654  - 时序驱动的放置阶段遇到错误。
错误：Xflow  - 程序映射返回错误代码2.中止流程执行...
make：*** [__xps / system_routed]错误1
这适用于FMC连接器上的ADC接口。
设计与我连接的第一个ADC正确构建和运行。
不同的ADC将LVDS对快速时钟信号路由到引脚H4和H5（LOC A10和B10），它们是FMC_LPC_CLK0_M2C。
显然，砂矿不喜欢这个，并抱怨上面显示的错误。
这是相关的UCF文件的片段：
ADI 9633的#Clock行##
NET adc_clk_in_p LOC =“A10”|
DIFF_TERM =“TRUE”|
IOSTANDARD =“LVDS_25”;
NET adc_clk_in_n LOC =“B10”|
DIFF_TERM =“TRUE”|
IOSTANDARD =“LVDS_25”;
NET adc_frame_p LOC =“K26”|
DIFF_TERM =“TRUE”|
IOSTANDARD =“LVDS_25”;
NET adc_frame_n LOC =“K27”|
DIFF_TERM =“TRUE”|
IOSTANDARD =“LVDS_25”;
##数据行ADI 9633 ##
NET adc_data_in_p [0] LOC =“A33”|
DIFF_TERM =“TRUE”|
IOSTANDARD =“LVDS_25”;
NET adc_data_in_n [0] LOC =“B33”|
DIFF_TERM =“TRUE”|
IOSTANDARD =“LVDS_25”;
NET adc_data_in_p [1] LOC =“E32”|
DIFF_TERM =“TRUE”|
IOSTANDARD =“LVDS_25”;
NET adc_data_in_n [1] LOC =“E33”|
DIFF_TERM =“TRUE”|
IOSTANDARD =“LVDS_25”;
NET adc_data_in_p [2] LOC =“J30”|
DIFF_TERM =“TRUE”|
IOSTANDARD =“LVDS_25”;
NET adc_data_in_n [2] LOC =“K29”|
DIFF_TERM =“TRUE”|
IOSTANDARD =“LVDS_25”;
NET adc_data_in_p [3] LOC =“K28”|
DIFF_TERM =“TRUE”|
IOSTANDARD =“LVDS_25”;
NET adc_data_in_n [3] LOC =“J29”|
DIFF_TERM =“TRUE”|
IOSTANDARD =“LVDS_25”;
这是BUFIO结构：
IBUFGDS i_clk_ibuf（
.I（adc_clk_in_p），
.IB（adc_clk_in_n），
.O（adc_clk_in_ibuf_s））;
BUFIO i_clk_gbuf（
.I（adc_clk_in_ibuf_s），
.O（adc_clk_in））;
BUFR＃（。BUFR_DIVIDE（“3”））i_clk_rbuf（
.CLR（1'b0），
.CE（1'b1），
.I（adc_clk_in_ibuf_s），
.O（adc_clk））;
有没有人有任何想法这个问题的解决方案是什么？



以下为原文

ERROR:Place:1073 - Placer was unable to create RPM[BUFIO_RPMs] for the component   axi_adc_4c_0/axi_adc_4c_0/USER_LOGIC_I/i_adc_4c/i_adc_if/i_clk_gbuf of type   BUFIO for the following reason.   The reason for this issue:   Some of the logic associated with this structure is locked. This should cause   the rest of the logic to be locked.  A problem was found where we should   place BUFIO   axi_adc_4c_0/axi_adc_4c_0/USER_LOGIC_I/i_adc_4c/i_adc_if/i_clk_gbuf off the   edge of the chip in order to satisfy the relative placement requirement of   this logic. The following components are part of this structure:ERROR:Pack:1654 - The timing-driven placement phase encountered an error.ERROR:Xflow - Program map returned error code 2. Aborting flow execution...make: *** [__xps/system_routed] Error 1This is for a ADC interface across the FMC connector. Design builds and functions properly with the first ADC that I interfaced it with. A different ADC routes an LVDS pair of a fast clock signal to pins H4 and H5 (LOC A10 and B10) which are FMC_LPC_CLK0_M2C. Evidently, the placer doesn't like this and complains with the error shown above.

This is the segment of the UCF file that's relevant:

#Clock lines for ADI 9633##NET adc_clk_in_p LOC = "A10" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25";NET adc_clk_in_n LOC = "B10" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25";NET adc_frame_p LOC = "K26" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25";NET adc_frame_n LOC = "K27" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25";##DATA lines for ADI 9633##NET adc_data_in_p[0] LOC = "A33" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25";NET adc_data_in_n[0] LOC = "B33" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25";NET adc_data_in_p[1] LOC = "E32" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25";NET adc_data_in_n[1] LOC = "E33" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25";NET adc_data_in_p[2] LOC = "J30" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25";NET adc_data_in_n[2] LOC = "K29" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25";NET adc_data_in_p[3] LOC = "K28" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25";NET adc_data_in_n[3] LOC = "J29" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25"; And here is the BUFIO structure:


  IBUFGDS i_clk_ibuf (    .I (adc_clk_in_p),    .IB (adc_clk_in_n),    .O (adc_clk_in_ibuf_s));  BUFIO i_clk_gbuf (    .I (adc_clk_in_ibuf_s),    .O (adc_clk_in));  BUFR #( .BUFR_DIVIDE ("3")) i_clk_rbuf (    .CLR (1'b0),    .CE (1'b1),    .I (adc_clk_in_ibuf_s),    .O (adc_clk)); Does anyone have any ideas what is the solution for this kind of problem?