[问答]

设计映射期间出错

1643 时钟

问答对人有帮助，内容完整，我也想知道答案 0 嗨，我们设计了一个包含XC7K410T-2FFG900I FPGA和phy（88e1111）的自定义硬件，我们正在尝试使用trimode ethernet mac启用phy。我们收到如下所示的展示位置错误。 “地点：906 - IO时钟网络驱动的组件无法放置和路由，因为位置限制导致时钟区域规则被违反.IO时钟网络由BUFIO驱动锁定到站点”BUFIO_X0Y12“由于此位置约束，只能驱动时钟区域“CLOCKREGION_X0Y3”以下组件通过已锁定到这些时钟区域内的网站驱动：trimac_block / gmii_rxd_int（锁定网站：ILOGIC_X0Y242 CLOCKREGION_X0Y4）trimac_block / gmii_rxd_int（锁定网站：ILOGIC_X0Y241 CLOCKREGION_X0Y4）trimac_block / gmii_rxd_int（锁定网站：ILOGIC_X0Y240 CLOCKREGION_X0Y4）trimac_block / gmii_rxd_int（锁定网站：ILOGIC_X0Y239 CLOCKREGION_X0Y4）trimac_block / gmii_rxd_int（锁定网站：ILOGIC_X0Y238 CLOCKREGION_X0Y4）trimac_block / gmii_rxd_int（锁定网站：ILOGIC_X0Y237 CLOCKREGION_X0Y4）trimac_block / gmii_rxd_int（锁定网站：ILOGIC_X0Y236 CLOCKREGION_X0Y4）trimac_block / gmii_rxd_int（锁定站点：ILOGIC_X0Y235 CLOCKREGION_X0Y4）trimac_block / gmii_rx_er_in t（锁定站点：ILOGIC_X0Y171 CLOCKREGION_X0Y3）trimac_block / gmii_rx_dv_int（锁定站点：ILOGIC_X0Y173 CLOCKREGION_X0Y3）请评估BUFIO和驱动组件的位置限制，以确保它们遵循架构的时钟区域规则。有关时钟区域规则的更多信息，请参阅体系结构用户指南。要使用部分路由设计调试您的设计，请允许mapper / placer完成执行（通过将环境变量XIL_PAR_DEBUG_IOCLKPLAC设置为1）.ERROR：Pack：1654 - 时序驱动的放置阶段遇到错误。“ 这里我们将gmii_rx_clk连接到bank15位置M18（SRCC引脚）和bank 16中的数据线。如何克服这个错误？我们可以添加任何属性，以便生成比特流？请帮助以上来自于谷歌翻译以下为原文 Hi, we have designed a custom hardware that contains XC7K410T-2FFG900I fpga and phy (88e1111),we are trying to enable the phy using trimode ethernet mac. we are getting placement error shown below. "Place:906 - Components driven by IO clock net can't be placed and routed because location constraints are causing the clock region rules to be violated. IO Clock net is being driven by BUFIO locked to site "BUFIO_X0Y12" Because of this location contraint, can only drive clock region "CLOCKREGION_X0Y3". The following components driven by have been locked to sites outside of these clock regions: trimac_block/gmii_rxd_int<7> (Locked Site: ILOGIC_X0Y242 CLOCKREGION_X0Y4) trimac_block/gmii_rxd_int<6> (Locked Site: ILOGIC_X0Y241 CLOCKREGION_X0Y4) trimac_block/gmii_rxd_int<5> (Locked Site: ILOGIC_X0Y240 CLOCKREGION_X0Y4) trimac_block/gmii_rxd_int<4> (Locked Site: ILOGIC_X0Y239 CLOCKREGION_X0Y4) trimac_block/gmii_rxd_int<3> (Locked Site: ILOGIC_X0Y238 CLOCKREGION_X0Y4) trimac_block/gmii_rxd_int<2> (Locked Site: ILOGIC_X0Y237 CLOCKREGION_X0Y4) trimac_block/gmii_rxd_int<1> (Locked Site: ILOGIC_X0Y236 CLOCKREGION_X0Y4) trimac_block/gmii_rxd_int<0> (Locked Site: ILOGIC_X0Y235 CLOCKREGION_X0Y4) trimac_block/gmii_rx_er_int (Locked Site: ILOGIC_X0Y171 CLOCKREGION_X0Y3) trimac_block/gmii_rx_dv_int (Locked Site: ILOGIC_X0Y173 CLOCKREGION_X0Y3) Please evaluate the location constraints of both the BUFIO and the components driven by to ensure that they follow the clock region rules of the architecture. For more information on the clock region rules, please refer to the architecture user's guide. To debug your design with partially routed design, please allow mapper/placer to finish the execution (by setting environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1). ERROR:Pack:1654 - The timing-driven placement phase encountered an error." here we have connected gmii_rx_clk to bank15 location M18(SRCC pin) and data lines in bank 16. how to overcome this error? any attributes we can add so that bit stream is generated?pls help 0
2018-11-8 11:32:58　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答举报 h1654155275.5835 相关推荐 • 使用CAAM安全密钥的磁盘加密，设备映射器在调用dmsetup时启动报错怎么解决？ 393 • FPGA重复读取同步SRAM所有地址数据出错可能是哪些原因？ 2250 • STM32 完全映射与部分映射的区别是什么呀？ 14925 • SP605上的MCB映射期间获取信号错误 909 • STM32F7 + QSPI (QUADSPI)内存映射读取操作失败的原因？如何解决？ 465 • MMU没映射的地址访问会怎么处理？ 3884 • 存储器映射是什么意思 940 • PCIE inbound映射，多个映射region的使用 2911 • CDT构建器报错程序无法编译不知道是什么原因？ 695 • STM32串口的部分映射与完全映射 54793 1个回答

答案对人有帮助，有参考价值 0 你好@ harikrishnani。 BUFIO时钟缓冲区仅限于一个bank / clock区域。在这种情况下，避免错误的选项是确保所有负载都驻留在一个bank / clock区域，或者使用可以驱动多个时钟区域的缓冲区。例如，BUFMR是一个多区域缓冲区，可以驱动多个时钟区域。时钟资源指南的“时钟连接摘要”部分应该有助于查找有关缓冲区连接和限制的更多信息。 http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf -------------------------------------------------- -----------------------不要忘记回答，kudo，并接受为解决方案.------------- -------------------------------------------------- ---------- 以上来自于谷歌翻译以下为原文 Hi @harikrishnani. The BUFIO clock buffer is limited to a single bank/clock region. With this being the case, the options to avoid the error would be to make sure that all the loads reside in one bank/clock region, or to use a buffer that can drive multiple clock regions. For example, a BUFMR is a multi-region buffer, and can drive multiple clock regions. The "Summary of Clock Connectivity" section of the Clocking Resources Guide should help find more information on buffer connectivity and limitations. http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf ------------------------------------------------------------------------- Don’t forget to reply, kudo, and accept as solution. -------------------------------------------------------------------------

2018-11-8 11:40:54 评论举报俞丽