请问BUFIO2和BUFG和ODDR2的解决方案是否用于时钟路由

你好
使用内部连接时，您可以直接使用相同的时钟，而无需ODDR2。
问候，萨蒂什-----------------------------------------------
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- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用的帖子。感谢.--
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在原帖中查看解决方案



以下为原文

Hi
 
When internal connection is used you can use the same clock directly with out the need of ODDR2.
Regards,

Satish

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做什么？
这些作业合法吗？
也许。
如果您的目标只是将输入信号连接到输出信号（在这种情况下它们是时钟的事实是无关紧要的）那么您可以这样做。
但是，如果您实际上计划将这些信号中的任何一个用作FPGA中的时钟，那么就没有。
即使您将输入连接到输出，输入信号和输出信号之间也会有很大且未知的延迟。
它将随工艺温度和电压以及实施的实施而变化很大。
那么，你为什么要这样做呢？
你想解决什么系统问题？
Avrum



以下为原文

To do what?
 
Are these assignments legal? Maybe. If your goal is just to connect an input signal to an output signal (the fact that they are clocks in this case is irrelevent) then you can do this. But, if you actually plan to use any of these signals as a clock within your FPGA, then no.
 
Even if you do connect the input to output, there will be a large and unknown delay between the input signal and the output signal. It will vary greatly over process temperature and voltage as well as implementation to implementation.
 
So, why do you want to do this? What system problem are you trying to solve?
 
Avrum

嗨Avrum！
我试图通过这个：
对此：
但没有成功。
如果需要查看，可以在附件中找到我的项目。
谢谢！
我试图通过这个：
SP605_SFP_SOLUTION.rar 3540 KB



以下为原文

Hi Avrum!
 
I am trying to pass from this:
 

 
 
to this:
 
 
 
 

 
 
 
but unsuccessfully. You can find my project in attachment if you need to take a look.
 
Thanks! 
 
I am trying to pass from this:
 
 
 
            SP605_SFP_SOLUTION.rar ‏3540 KB

我完全失去了你......
你附上的图纸与ODDR有什么关系？
ODDR是一个专用于从FPGA中驱动双倍数据速率信号的触发器 -  ODDR的输出只能到达OBUF，从那里，它不能再在FPGA内部使用。
至于BUFIO和BUFG，你可以在你的绘图中使用它们，从我所看到的，它们在那里是正确的。
BUFG的输出是一个全局时钟，可以驱动FPGA内的所有逻辑，包括GTP和两个内核的所有输入时钟。
你为什么要删除它们？
Avrum



以下为原文

I have completely lost you...
 
What does the drawing you attached have anything to do with ODDRs? An ODDR is a flip-flop dedicated to driving a double data rate signal out of the FPGA - the output of the ODDR can only go to an OBUF and from there, it can no longer be used inside the FPGA.
 
As for the BUFIO and BUFG, you have them in your drawing, and, from what I can see, they are correct there. The output of the BUFG is a global clock and can drive all logic within the FPGA, including all the input clocks of the GTP and both cores. Why are you trying to remove them?
 
Avrum
 

嗨Avrum！
1000BASE-X内核具有驱动gmii_rx_clock的ODDR2元素（来自示例设计）： 
- 这实例化DDR输出寄存器。
这是一个很好的方式 
- 驱动GMII输出时钟，因为时钟到PAD的延迟将是 
- 与从IOB输出触发器驱动的数据相同。
这是 
- 设置为产生倒置时钟w.r.t.
userclk2使时钟 
- 上升沿出现在GMII数据的中心。 
rx_clk_ddr_iob0：ODDR2 
港口地图（ 
Q => gmii_rx_clk0， 
C0 => userclk2， 
C1 => not_userclk2， 
CE =>'1'， 
D0 =>'0'， 
D1 =>'1'， 
R =>'0'， 
S =>'0' 
）;
因为我在内部使用gmii接口和MAC内核，所以我不需要像设计那样将这个时钟带到输出板。
那可能是什么解决方案呢？
通过转让直接连接还是我之间放一些东西？
关于BUFIO2 + BUFG问题，我已经解决了。
谢谢！



以下为原文

Hi Avrum!
 
The 1000BASE-X core has this ODDR2 element driving the gmii_rx_clock (from example design):
 
   -- This instantiates a DDR output register.  This is a nice way to   -- drive the GMII output clock since the clock-to-PAD delay will the   -- same as that of data driven from an IOB Ouput flip-flop.  This is   -- set to produce an inverted clock w.r.t. userclk2 so that clock   -- rising edge appears in the centre of GMII data.   rx_clk_ddr_iob0 : ODDR2   port map(      Q  => gmii_rx_clk0,      C0 => userclk2,      C1 => not_userclk2,      CE => '1',      D0 => '0',      D1 => '1',      R  => '0',      S  => '0'   ); 
since I am using the gmii interface internally with the MAC core, I do not need to bring this clock to an output pad as the example design does. So what could be the solution? A direct connection by assignment or shall I put something in between?
 
For what concerns the BUFIO2+BUFG issue, I have solve it.
 
Thanks!
 

你好
使用内部连接时，您可以直接使用相同的时钟，而无需ODDR2。
问候，萨蒂什-----------------------------------------------
--- --------------------------------------------请注意
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用的帖子。感谢.--
---------------------------- ---------------------
----------------------



以下为原文

Hi
 
When internal connection is used you can use the same clock directly with out the need of ODDR2.
Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------

嗨yenigal！
我应该做以下两项任务中的哪一项？
assigngmii_rx_clk0 = userclk2;
assigngmii_rx_clk0 = not_userclk2;
谢谢！



以下为原文

Hi yenigal!
 
which one of the following two assignment should I make?
 
assign gmii_rx_clk0 = userclk2;
 
assign gmii_rx_clk0 = not_userclk2;
 
Thank you!

嗨Linkaiyu，
正如您在使用内部接口时的核心框图集成中所看到的那样。
两个内核都以125MHz的时钟频率运行，并且不需要将GMII时钟连接到输出。
你可以简单地忽略那个时钟。
问候，萨蒂什-----------------------------------------------
--- --------------------------------------------请注意
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用的帖子。感谢.--
---------------------------- ---------------------
----------------------



以下为原文

Hi Linkaiyu,
 
As you can see in the integration of the cores block diagram when internal interfaces are used.
 
Both the cores runs with the 125MHz clock frequency and there is no need of this GMII Clock connection to the output.
 
You can simple ignore that clock.
Regards,

Satish

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Give Kudos to a post which you think is helpful.
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