ODDR2行为模拟错误

该问题与模型的delta延迟有关，并且仅在行为模拟中发生。为了解决这个问题，可以运行Post Translate模拟或者可以将“wire”添加到ODDR2的Clock中，以下是一个示例
.Data_IN_Del ODDR_inst0：ODDR2generic map（DDR_ALIGNMENT =>“C0”，SRTYPE =>“ASYNC”）端口映射（Q => oddr2_out（0），C0 => CLK，C1 => CLK_N，CE => CE，D0 =>
Data_IN_Del，D1 =>'0'，R =>复位，S =>'0'）;此附加网络添加的增量延迟不会影响硬件的时序或性能，因此可以在执行期间安全地保留
该设计。
--------------------------------------------------
-----------------------不要忘记回答，kudo，并接受为解决方案.-------------
--------------------------------------------------
----------
在原帖中查看解决方案



以下为原文

The issue is related to the delta delays of the model and only occurs in the behavioural simulations.

To work around it a Post Translate simulation can be run or a "wire" can be added to the Clock of the ODDR2, the following is an example.


Data_IN_Del <= Data_IN  -- Wire Added

ODDR_inst0 : ODDR2
generic map(
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC")
port map (
Q => oddr2_out(0),
C0 => CLK,
C1 => CLK_N,
CE => CE,
D0 => Data_IN_Del,
D1 => '0',
R => Reset,
S => '0'
);

The delta delay added by this additional net will not affect the timing or performance in Hardware and so it can be safely left in during implementation of the design.
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------View solution in original post

移动的线程链接已断开。
这个帖子现在在哪里？



以下为原文

The moved thread link is broken.  Where is this thread now? 

我也遇到了ODDR2模型的奇怪行为。
而且链接仍然破裂......



以下为原文

I'm also experiencing wierd behavior of the ODDR2 model.
And the link is still broken...

我也有这个问题。
一模一样。
某处有解决方案吗？
我无法在论坛的任何地方找到移动的帖子。



以下为原文

I also have this very problem. Exactly the same. Is there a solution somewhere? I cannot find the moved post anywhere in the forum.

该问题与模型的delta延迟有关，并且仅在行为模拟中发生。为了解决这个问题，可以运行Post Translate模拟或者可以将“wire”添加到ODDR2的Clock中，以下是一个示例
.Data_IN_Del ODDR_inst0：ODDR2generic map（DDR_ALIGNMENT =>“C0”，SRTYPE =>“ASYNC”）端口映射（Q => oddr2_out（0），C0 => CLK，C1 => CLK_N，CE => CE，D0 =>
Data_IN_Del，D1 =>'0'，R =>复位，S =>'0'）;此附加网络添加的增量延迟不会影响硬件的时序或性能，因此可以在执行期间安全地保留
该设计。
--------------------------------------------------
-----------------------不要忘记回答，kudo，并接受为解决方案.-------------
--------------------------------------------------
----------



以下为原文

The issue is related to the delta delays of the model and only occurs in the behavioural simulations.

To work around it a Post Translate simulation can be run or a "wire" can be added to the Clock of the ODDR2, the following is an example.


Data_IN_Del <= Data_IN  -- Wire Added

ODDR_inst0 : ODDR2
generic map(
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC")
port map (
Q => oddr2_out(0),
C0 => CLK,
C1 => CLK_N,
CE => CE,
D0 => Data_IN_Del,
D1 => '0',
R => Reset,
S => '0'
);

The delta delay added by this additional net will not affect the timing or performance in Hardware and so it can be safely left in during implementation of the design.
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

jheslip写道：这个问题与模型的delta延迟有关，并且只发生在行为模拟中。为了解决这个问题，可以运行Post Translate模拟，或者可以将“wire”添加到ODDR2的Clock中，以下
是一个例子.Data_IN_Del ODDR_inst0：ODDR2generic map（DDR_ALIGNMENT =>“C0”，SRTYPE =>“ASYNC”）端口映射（Q => oddr2_out（0），C0 => CLK，C1 => CLK_N，CE => CE，
D0 => Data_IN_Del，D1 =>'0'，R =>复位，S =>'0'）;此附加网络添加的增量延迟不会影响硬件的时序或性能，因此可以安全地保留
在设计实施期间。
如何而不是解决方法，修复fscking模型？
破碎的模型导致设计师的信心降低，我的意思是客户。
----------------------------是的，我这样做是为了谋生。



以下为原文

jheslip wrote:
The issue is related to the delta delays of the model and only occurs in the behavioural simulations.

To work around it a Post Translate simulation can be run or a "wire" can be added to the Clock of the ODDR2, the following is an example.


Data_IN_Del <= Data_IN -- Wire Added

ODDR_inst0 : ODDR2
generic map(
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC")
port map (
Q => oddr2_out(0),
C0 => CLK,
C1 => CLK_N,
CE => CE,
D0 => Data_IN_Del,
D1 => '0',
R => Reset,
S => '0'
);

The delta delay added by this additional net will not affect the timing or performance in Hardware and so it can be safely left in during implementation of the design.

How about instead of the workaround, fix the fscking model?
 
Broken models lead to a reduction in the confidence of designers, I mean, customers.
----------------------------Yes, I do this for a living.

我的模拟失败时也找到了这个帖子。
如果你问我，这是一个非常糟糕的解决方法。



以下为原文

I also found this thread when my simulation failed.  This is a pretty crappy workaround if you ask me.