请问哪些时钟区域映射到哪个BUFIO2区域？

您正在使用的器件/封装的封装文件显示每个引脚所在的BUFIO2时钟区域。请参阅http://www.xilinx.com/support/packagefiles/spartan-6-pkgs.htm
Avrum
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以下为原文

The package files for the device/package you are using show which BUFIO2 clock region each pin is in. See http://www.xilinx.com/support/packagefiles/spartan-6-pkgs.htm
 
Avrum
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Spartan-6器件的核心是基于列的，与之前的Virtex系列一样。
因此，织物区域具有沿中间（左/右）分开并跨越一定数量的CLB行的时钟区域。
但是，与Virtex器件不同，它们不是倒装芯片器件;
他们使用线焊技术。
因此，IOB位于FPGA外围的环中。
因此，IOB不在结构时钟区域中;
他们有自己的时钟区域。
这些时钟区域由I / O时钟网络的跨度定义，其中有两种类型 - 由BUFIO2驱动的那些和由BUFPLL驱动的那些。
由BUFIO驱动的每个都是跨越设备一个边缘的一半的网络（因此设备的4个边缘中的每一个上有两个存储体）。
BUFPLL网络是每边一个（所以它们有4个区域）。
在每个BUFIO2区域内，有4个BUFIO2时钟网络，每个由BUFIO2驱动，BUFIO2又可以由位于每个边缘中心的几个时钟IOB中的一个驱动（一些直接，一些使用反向连接）
）。
所有这些都记录在Spartan 6时钟用户指南（UG382）中，从“I / O时钟基础设施”部分开始。
Avrum



以下为原文

The core of the Spartan-6 devices are column based, like previous Virtex generations. As such, the fabric area has clock regions that are split down the middle (left/right) and span a certain number of CLB rows.
 
However, unlike the Virtex devices, they are not flip-chip devices; they use wire bond technology. As such, the IOBs are located in a ring around the periphery of the FPGA. Therefore, the IOBs are not in the fabric clock regions; they have clock regions of their own. These clock regions are defined by the spans of the I/O clock networks, of which there are two types - those driven by BUFIO2 and those driven by BUFPLL. Those driven by the BUFIO are each a  network that spans one half of one edge of the device (thus two banks on each of the 4 edges of the device). The BUFPLL networks are one per side (so there are 4 regions for them).
 
Within each BUFIO2 region, there are 4 BUFIO2 clock networks, each driven by a BUFIO2, which, in turn, can be driven by one of several clock capable IOBs that live in the center of each edge (some directly, and some using inverted connections).
 
All of this is documented in the Spartan 6 Clocking User Guide (UG382) starting with the section "I/O Clocking Infrastructure".
 
Avrum
 
 

avrumw写道：
Spartan-6器件的核心是基于列的，与之前的Virtex系列一样。
因此，织物区域具有沿中间（左/右）分开并跨越一定数量的CLB行的时钟区域。
但是，与Virtex器件不同，它们不是倒装芯片器件;
他们使用线焊技术。
因此，IOB位于FPGA外围的环中。
因此，IOB不在结构时钟区域中;
他们有自己的时钟区域。
这些时钟区域由I / O时钟网络的跨度定义，其中有两种类型 - 由BUFIO2驱动的那些和由BUFPLL驱动的那些。
由BUFIO驱动的每个都是跨越设备一个边缘的一半的网络（因此设备的4个边缘中的每一个上有两个存储体）。
BUFPLL网络是每边一个（所以它们有4个区域）。
感谢历史课。
不太相关，但......
在每个BUFIO2区域内，有4个BUFIO2时钟网络，每个由BUFIO2驱动，BUFIO2又可以由位于每个边缘中心的几个时钟IOB中的一个驱动（一些直接，一些使用反向连接）
）。
理解......
所有这些都记录在Spartan 6时钟用户指南（UG382）中，从“I / O时钟基础设施”部分开始。
是的，但文档实际上并没有回答我的问题。
我知道如何从GCLK引脚驱动时钟输入以及如何实例化BUFIO2以及所有这些。
这不是我遇到问题的时钟输入。
我在一些引脚上有一批输入信号进入FPGA。
这些引脚需要位于BUFIO2区域。
我如何知道BUFIO2区域中的哪些引脚？
例如，因为没有任何内容可以说明TL BUFIO2区域中的IO引脚是什么。
----------------------------是的，我这样做是为了谋生。



以下为原文

avrumw wrote:
The core of the Spartan-6 devices are column based, like previous Virtex generations. As such, the fabric area has clock regions that are split down the middle (left/right) and span a certain number of CLB rows.
 
However, unlike the Virtex devices, they are not flip-chip devices; they use wire bond technology. As such, the IOBs are located in a ring around the periphery of the FPGA. Therefore, the IOBs are not in the fabric clock regions; they have clock regions of their own. These clock regions are defined by the spans of the I/O clock networks, of which there are two types - those driven by BUFIO2 and those driven by BUFPLL. Those driven by the BUFIO are each a  network that spans one half of one edge of the device (thus two banks on each of the 4 edges of the device). The BUFPLL networks are one per side (so there are 4 regions for them).
 
Thanks for the history lesson. Not really relevant, though ...
 
Within each BUFIO2 region, there are 4 BUFIO2 clock networks, each driven by a BUFIO2, which, in turn, can be driven by one of several clock capable IOBs that live in the center of each edge (some directly, and some using inverted connections).
 
Understood ...
 
All of this is documented in the Spartan 6 Clocking User Guide (UG382) starting with the section "I/O Clocking Infrastructure". 

Yes, but the docs don't actually answer my question.
 
I know how to drive the clock inputs from GCLK pins and how to instantiate the BUFIO2 and all of that. It's not the clock inputs with which I have a problem.
 
I have a batch of input signals coming into the FPGA on some pins. These pins need to be in the BUFIO2 region. How do I know which pins are in which BUFIO2 region? 
 
Because there's nothing that says what IO pins are in the TL BUFIO2 region, for example.
 
----------------------------Yes, I do this for a living.

您正在使用的器件/封装的封装文件显示每个引脚所在的BUFIO2时钟区域。请参阅http://www.xilinx.com/support/packagefiles/spartan-6-pkgs.htm
Avrum



以下为原文

The package files for the device/package you are using show which BUFIO2 clock region each pin is in. See http://www.xilinx.com/support/packagefiles/spartan-6-pkgs.htm
 
Avrum

avrumw写道：
您正在使用的器件/封装的封装文件显示每个引脚所在的BUFIO2时钟区域。请参阅http://www.xilinx.com/support/packagefiles/spartan-6-pkgs.htm
Avrum
谢谢，这正是我正在寻找的。
这种事情需要在PlanAhead中。
因为它完全不直观。
----------------------------是的，我这样做是为了谋生。



以下为原文

avrumw wrote:
The package files for the device/package you are using show which BUFIO2 clock region each pin is in. See http://www.xilinx.com/support/packagefiles/spartan-6-pkgs.htm
 
Avrum

Thanks, that's exactly what I'm looking for.
This sort of thing needs to be in PlanAhead. Because it's entirely non-intuitive.
----------------------------Yes, I do this for a living.