Spartan-6 BUFIO2/BUFIO2FB放置限制在哪里记录？

嗨Spartan-6时钟专家，
我遇到了一个稍微令人烦恼的问题，我认为我可以在设计中使用任何GCLK引脚作为反馈引脚，利用DCM将时钟偏移到外部反馈焊盘。
但是，我太天真了，BUFIO2FB位置（右？）仅限于用于输入时钟（BUFIO2）的成对GCLK输入的另一半。
更准确地说，这是设计（剥离与此问题无关的所有内容）：
库IEEE;使用IEEE.std_logic_1164.all;库unisim;使用unisim.vcomponents.all;实体a是端口（clk_in：在std_logic中;  - 一个GCLK引脚，当然clk_out：out std_logic; clk_fb：在std_logic中）;
- 这是哪个引脚？
甚至在同一个银行上也没有任何GCLK引脚...结束实体a; a的架构a_0是信号clk_in_1，clk_in_2，clk_fb_1，clk_fb_2，clk_x，clk：std_logic;开始x1：IBUF端口映射（I => clk_in，O =>
clk_in_1）;
x2：BUFIO2通用映射（DIVIDE_BYPASS => true，I_INVERT => false，USE_DOUBLER => false）端口映射（I => clk_in_1，DIVCLK => clk_in_2，IOCLK => open，SERDESSTROBE => open）;
x3：IBUF端口映射（I => clk_fb，O => clk_fb_1）;
x4：BUFIO2FB通用映射（DIVIDE_BYPASS => true）端口映射（I => clk_fb_1，O => clk_fb_2）;
x5：DCM_SP通用映射（CLK_FEEDBACK =>“1X”，CLKOUT_PHASE_SHIFT =>“FIXED”，PHASE_SHIFT => 0）端口映射（CLKIN => clk_in_2，CLKFB => clk_fb_2，CLK0 => clk_x，DSSEN =>'0'，
RST =>'0'，PSINCDEC =>'0'，PSEN =>'0'，PSCLK =>'0'）;
x6：BUFG端口映射（I => clk_x，O => clk）;
- 驱动clk_out w /内部clk x7的最小偏斜：ODDR2端口映射（Q => clk_out，C0 => clk，C1 =>不clk，CE =>'1'，D0 =>'1'，D1 =>
'0'，R =>'0'，S =>'0'）;
- 在更完整的实际设计中，clk也有其他负载，当然......结束a_0;
更清楚地提出我的问题：
1.鉴于将clk_in分配给其中一个GCLK引脚，哪些引脚可以用于clk_fb？
特别是，对于单端时钟，只有一种可能性，或两种或更多？
对于差分时钟（不是上面的例子）是不可能的，还是有一个可能的分配？
2.这是否在Xilinx文档的某处清楚地记录了？
我认为事后看来它在UG382中有点暗示，例如第113页（版本1.7），“为了获得最佳放置，反馈时钟的输入焊盘必须放在差分对上。”
但我没有看到任何地方，它解释这是一个真正的限制，其他放置不可能路由。
甚至这个设备也不适用于DCM以及PLL。
我应该解释一下，如果anwer是运行输入时钟并通过另外两个BUFG反馈给DCM而不是BUFIO2 / BUFIO2FB（我不知道这是否可能），我希望避免这样，因为我会
完全脱离BUFG的设计。
如果某人有答案我应该在文档中阅读这个，那将不胜感激。
或者如果它不在文档中并且Xilinx人员正在阅读此内容，您是否可以将其添加到下一个doc发布的更改请求中？
谢谢！
- 杰拉德



以下为原文

hi Spartan-6 clocking experts,
  I have encountered a mildly vexing problem, I thought that I could use any GCLK pin for the feedback pin in a design utilizing DCM to deskew a clock to external feedback pad. But, I was too naive, the BUFIO2FB placement is (right?) restricted to the other half of the paired GCLK input used for the input clock (BUFIO2).
  More precisely, here is the design (stripped of everything not relevant to this issue):

library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity a is
   port (
      clk_in: in std_logic;             -- a GCLK pin, of course
      clk_out: out std_logic;
      clk_fb: in std_logic );           -- which pins can this be? not any GCLK pin even on same bank...
end entity a;

architecture a_0 of a is
   signal clk_in_1, clk_in_2, clk_fb_1, clk_fb_2,
      clk_x, clk: std_logic;
begin

   x1: IBUF port map(I => clk_in, O => clk_in_1);
   x2: BUFIO2 generic map(DIVIDE_BYPASS => true, I_INVERT => false, USE_DOUBLER => false)
      port map(I => clk_in_1, DIVCLK => clk_in_2,
               IOCLK => open, SERDESSTROBE => open);

   x3: IBUF port map(I => clk_fb, O => clk_fb_1);
   x4: BUFIO2FB generic map(DIVIDE_BYPASS => true)
      port map(I => clk_fb_1, O => clk_fb_2);
   
   x5: DCM_SP generic map(CLK_FEEDBACK => "1X", CLKOUT_PHASE_SHIFT => "FIXED",
                  PHASE_SHIFT => 0)
      port map(CLKIN => clk_in_2, CLKFB => clk_fb_2, CLK0 => clk_x,
               DSSEN => '0', RST => '0', PSINCDEC => '0', PSEN => '0', PSCLK => '0');
   x6: BUFG port map(I => clk_x, O => clk);

   -- drive clk_out w/ minimal skew from internal clk
   x7: ODDR2 port map(Q => clk_out, C0 => clk, C1 => not clk,
                      CE => '1', D0 => '1', D1 => '0', R => '0', S => '0');
   -- in more complete real design clk has other loads too, of course...
   
end a_0;


    Putting my questions more crisply:
1. Given an assignment of clk_in to one of the GCLK pins, which pins exactly may be used for clk_fb? In particular, for single-ended clocks is there only one possibility or two, or more? For differential clocks (not the example above) is is impossible, or is there one possible assignment?

2. Is this clearly documented somewhere in the Xilinx docs? I think that with hindsight it is sort of hinted at in UG382, for instance page 113 (ver. 1.7), "For optimal placement, the input pad for the feedback clock must be placed on the
differential pair." But I don't see anyplace where it explains this is a real restriction that other placements are not possible to route. Nor even that thisadvice applies to DCM as well as PLL.

   I should explain if the anwer is to run the input clock and feedback to the DCM through two more BUFG's rather than uing BUFIO2 / BUFIO2FB (I don't know if that is even possible), I would wish to avoid that because I'll run out of BUFG's in the full design.

  If someone has an answer where I should have read this in the documentation, that would be appreciated. Or if it's not in the documentation and Xilinx people are reading this, could you add it to change request for next doc release? Thank you!

    - Gerard