Spartan6中的ODDR2使用Planahead设置和重置冲突

据我所知，您不能在当前版本的Xst中使用端口映射中的函数。
定义一个新信号并分配clk5m_n。



以下为原文

As far as I know, you can't use functions in port maps in the current version of Xst.
 
Define a new signal and assign clk5m_n <= not clk5m.

嗨joelby你的答案！
我已经读过ODDR2有内部逆变器，它比外部逆变器好
（例如参见http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan6-PLL-BASE-Phase-aligned-Clocks/m-p/169218#M12632）
我认为这个问题只出现在Planahead上，但有Set和Reset引脚！
ODDR2原语具有SET和RESET连接，但Planahead软件表示存在冲突！
你怎么看？
非常感谢
马尔科
熔点



以下为原文

Hi joelby for your answer!
I have read that ODDR2 has internal inverter that it is better than external one
(see for example  http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan6-PLL-BASE-Phase-aligned-Clocks/m-p/169218#M12632 ) 
 
I think that the problem is only on Planahead but with Set and Reset pins! The ODDR2 primitive has either SET and RESET connections, but Planahead software said that there is a conflict!
What do you think?
Thanks a lot
Marco
mp

马可，
在所有Spartan-6文档中，似乎ODDR2和ODDR2原语内部都有时钟输入反相器。
这是过于简单化了。
实际上，逆变器不位于Spartan-6器件中ODDR2（或IDDR2）模块的内部。
逆变器实际上位于ODDR2块附近的开关矩阵中。
使情况更加复杂的是一点点互连的阴谋。
BUFG输出可以连接到IDDR2 / ODDR2模块的.C0和.C1输入，包括开关矩阵中的反相器。
ISE将完成将BUFG输出连接到IDDR2 / ODDR2时钟输入所需的所有“魔力”，并反转其中一个输入（如果这是您的代码推断的话）。
另一方面，BUFIO2时钟缓冲器输出只能连接到IDDR2 / ODDR2时钟输入中的一个。
要连接BUFIO2的.C0和.C1时钟输入，必须使用两（2）个BUFIO2缓冲器。
如果您这样做，则应将其中一个BUFIO2缓冲区配置为反相缓冲区。
我不认为BUFIO2可以连接到开关矩阵中的逆变器，但好消息是这不是必需的 -  BUFIO2有自己的逆变器。
我在此论坛帖子中通过反复试验证明了这一点，我的结果得到了直接了解互连限制的Xilinx应用程序人员的确认。
这有助于您更好地理解Spartan-6 IDDR2 / ODDR2模块吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
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以下为原文

Marco,
 
In all the Spartan-6 documentation, it seems there are clock input inverters internal to ODDR2 and ODDR2 primitives.  This is an oversimplification.  The inverters are actually *not* located internal to the ODDR2 (or IDDR2) blocks in Spartan-6 devices.  The inverters are actually located in a switch matrix near the ODDR2 block.
 
Further complicating the situation is a little bit of interconnect intrigue.  A BUFG output can connect to both .C0 and .C1 inputs to IDDR2/ODDR2 blocks, including the inverters in the switch matrix.  ISE will do all the "magic" necessary to connect a BUFG output to the IDDR2/ODDR2 clock inputs, and invert one of the inputs as well (if that is what your code infers).
 
On the other hand, a BUFIO2 clock buffer output can connect to only one of the IDDR2/ODDR2 clock inputs.  To connect to both .C0 and .C1 clock inputs from BUFIO2, you must use two (2) BUFIO2 buffers.  If you are doing this, then one of the BUFIO2 buffers should be configured as an inverting buffer.  I don't think the BUFIO2 can connect to the inverter in the switch matrix, but the good news is that this is not necessary -- the BUFIO2 has its own inverter.
 
I demonstrated this by trial and error in this forum thread, and my results were confirmed by Xilinx apps folks who had direct knowledge of the interconnect restrictions.
 
Does this help you understand the Spartan-6 IDDR2/ODDR2 blocks a bit better?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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嗨鲍勃
谢谢您的回答
对于时钟我没有任何问题：我使用DCM生成时钟（我想内部BUFG）和ISE不会给我任何问题。
同时使用ODDR2的复位和设置引脚，我对ISE没有任何问题，我的项目适合。
但是，当我使用Planahead连接物理外部引脚时，该程序向我发送错误消息，因为（我认为在OSRUSED.OUT重放的功能中）SET和RESET引脚被看作连接在一起
为什么？
ODDR2原语具有不同的SET和RESET引脚，但Planahead不知道这种差异！
我想Planahead有一个Bug！
熔点



以下为原文

Hi Bob
Thank you for your answer
For the clock I don't have any problem: I use a DCM to generate clocks (I suppose with internal BUFG) and ISE doesn't give me any problem.
Also with Reset and Set pins of ODDR2 I don't have any problem with ISE and my project fits.
But when I use Planahead to connect phisical external pins, this program sends me a message of error because (I suppose in function of the OSRUSED.OUT replay) SET and RESET pins are seen connected together
Why?
The ODDR2 primitive has different SET and RESET pins but Planahead doesn't know this difference!!
I suppose that Planahead has a Bug!
mp

马可，
如果PlanAhead是错误的唯一途径，那么提交Webcase是有序的。
您似乎已经证明，在没有PlanAhead的情况下应该工作（并且确实有效）的配置在使用PlanAhead实现时会引发错误。
这是Webcase支持团队复制错误所需的关键信息。
通过您的调试工作来指导他们，让网络邮件支持人员隔离和识别此错误将为所有跟随您的路径的设计人员提供服务。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Marco,
 
If PlanAhead is the only path to an error, then submitting a webcase is in order.
 
You seem to have demonstrated that a configuration which should work (and does work) without PlanAhead will provoke an error when implemented with PlanAhead.  This is the critical information the webcase support team needs to replicate your error.  With your debugging work to guide them, getting this bug isolated and identified by the webcase support folks will be providing a service for all the designers who follow in your path.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

嗨鲍勃
非常感谢您的帮助。
我发送了一些邮件给区域Xilinx分销商的现场工程师，他说他用ISE 13.4和新的Planahead测试了ODDR2原语并且没有错误。
我仍然使用13.1 ISE版本（可能）旧的Planahead版本。
可能这个错误已得到修复。
当我下载新的ISE软件时，我将测试ODDR2原语
问候
马尔科
熔点



以下为原文

Hi Bob
Thank you very much for your help.
I sent some mails to field engineer of Regional Xilinx Distributor and he said that he tested ODDR2 primitive with ISE 13.4 plus new Planahead and there was no error. I still work with 13.1 ISE version with (probably) old Planahead version.
Probably this error has been fixed.
When I download new ISE software,  I will test ODDR2 primitive
Regards
Marco
mp