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我有一个基于Spartan 3A的设计。
我的客户退回了一块板(600多块产品中有1块),当温度达到45摄氏度左右时,它会失效。温度非常具体,44度工作,46度失效,这是完全可重复的 。 在成品中,电路板强制冷却通常不会超过35度,因此其他电路板可能具有类似的不稳定性。 FPGA旁边有一个温度传感IC,因此我有一个相当好的温度指示。 当我对FPGA设计进行非常小的改动时,不会影响设计的操作部分并加载该熔丝图,那么温度问题就会发生变化。 我只是通过输出缓冲器将逻辑高电平门控到未使用的引脚,现在器件在65摄氏度左右失效,再次非常可重复。 我不确定FPGA中是否存在故障节点,或者我的FPGA设计是否存在问题,导致延迟导致不稳定。 我的想法是,当我改变温度以消除设备时,我能以某种方式以某种方式测试Spartan 3A节点上的所有节点吗? 客户认为他可能有另一块板在54摄氏度左右失效。 任何输入赞赏。 问候 戴夫 以上来自于谷歌翻译 以下为原文 I have a design based on Spartan 3A. I have had a board returned (1 out of over 600 produced) by my customer which fails when the temperature reaches around 45 degrees C. The temperature is very specific, at 44 degrees it works and at 46 degrees it fails, this is completely repeatable. In the finished product the board is force cold usually would never get above 35 degrees so other boards may have similar instability. There is a temperature sensing IC alongside the FPGA so I have a fairly good indication of temperature. When I made a very small change to the FPGA design, something that does not affect the operational part of the design and load this fusemap then the temperature problem changes. I simply gated a logic high through an output buffer to an unused pin, now the device fails around 65 degrees C, again very repeatable. I am not sure whether there is a faulty node within the FPGA or if I have a problem with my FPGA design with delays causing instability. My thought is can I somehow test all on the nodes of the Spartan 3A in some way while I change the temperature to eliminate the device? Customer thinks he may have another board which fails at around 54 degrees C. Any input appreciated. regards Dave |
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6个回答
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戴夫,
结温是多少? 案例温度告诉我们什么。 -C部件的额定值符合锡至85C结。 在此之上,他们可能无法满足他们的速度规格。您的时间报告中有多少松懈? 如果正面松弛不足以导致系统抖动,那么您可能会失败,因为您没有受到严格限制。 每个设备都会根据流程随机变化。 修改设计,无论多么简单,都会移动路径(地点和路线会发生变化),因此您的问题会四处移动,但不能保证完全消失。 这是一个直接的标志(暗示)你被不恰当地约束。 Austin Lesea主要工程师Xilinx San Jose 以上来自于谷歌翻译 以下为原文 Dave, What is the junction temperature? Case temperature tells us nothing. -C parts are rated to meet tinming to 85C junction. Above that, they may not meet their speed specifications. How much slack did you have in your timing reports? If the posistive slack is insufficient for system jitter, you may be failing because you are not ptroperly constrained. Every device will have random variations in the timing based on process. Revising the design, no matter how simple, will move paths (place and route will change), so your problem will move around, but not be guaranteed to go away completely. This is a direct sign (hint) you are improperly constrained. Austin Lesea Principal Engineer Xilinx San Jose |
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嗨奥斯汀
谢谢你的回复! 结温必定非常低,无论如何我使用的是工业部件,部件号为XC3S200A-4FTG256I。 45摄氏度的温度远低于工业最高温度,外壳温度与温度传感器温度一致。 在环境中,大约22摄氏度,整个地段在33摄氏度左右,没有强制冷却,我们必须使用暖风机来升高温度并使其失效,这不是设备上的苛刻应用。 我完全接受你说的话,我还没有通过约束程序。 我们所有其他库存板,经过测试,在温度超过80摄氏度时都能正常工作,但它们并没有完全失败,但我们不想超过这种情况,以免损坏它们。 有没有办法通过工厂测试或生成特殊的Fusemap来测试电路中的实际芯片设备? 问候 戴夫 以上来自于谷歌翻译 以下为原文 Hi Austin Thanks for you reply! The junction temperature must surely be very low and I am using an industrial part anyway, part number is XC3S200A-4FTG256I. The temperature of 45 degrees C is so far below the Industrial maximum temperature and the case temperature is consistent with the temperature sensor temperature. In ambient, around 22 degrees C the whole lot sits around 33 degrees C with no forced cooling, we have to use a warm air blower to raise the temperature and make it fail, this is not a demanding application on the device. I thoroughly accept what you say and I have not been through a constraint process yet. All of our other stock boards, 15 tested, work perfectly at temperatures over 80 degrees C, they did not fail at all but we did not want to go above this case temp for fear of damaging them. Is there any way to test the actual silicon device in circuit, by a factory test or by generating a special Fusemap? regards Dave |
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戴夫,
我们是基于静态RAM(没有保险丝)。 损坏可能发生在超过125℃的Tj之外,因此我怀疑您可能会将设备放置在测试室中以将操作温度升高到该值以下,从而损坏设备。 在你有数千个单元工作之前,9小样本(你是什么)并不是有效设计的证据。 您缺少约束,或者您的约束不正确(不要正好考虑系统抖动)。 我将放置和布线设计,系统抖动预算为500 ps,然后仔细检查详细时序报告的每一行。 如果您的系统抖动小于500 ps,并且设计受到适当限制,则应该在高达Tj为100 C(工业上限)时无误操作。 Austin Lesea主要工程师Xilinx San Jose 以上来自于谷歌翻译 以下为原文 Dave, We are static RAM based (have no fuses). Damage may occur beyond a Tj of 125C, so I doubt you may harm the devices by placing them in a test chamber to raise the operating temperature below that value. Until you have thousands of units working, a small sample size 9(what you) is no evidence of a valid design. You are missing a constraint, or the constraints you have are incorrect (do not propely account for system jitter). I would place and route the design with a system jitter budget of 500 ps, and then carefully check each and every line of the verbose timing report. If your system jitter is less than 500 ps, and the design is properly constrained, you should operate error free up to a Tj of 100 C (Industrial upper limit). Austin Lesea Principal Engineer Xilinx San Jose |
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嗨奥斯汀
公认。 它只是说这一块板的表现与其他板不同,但据说它是在1年前制造的,设备的Lot码与我们拥有的其他10块板不同,所有板都有相同的Lot码。 这是英国晚上10点,所以我明天到办公室时会实施你的建议。 电路板上还有其他设备可能不会对较高的温度感到宽容,我会检查。 我希望有一个快速的方法来证明这只是一个有缺陷的设备(或不是),但看起来我将不得不做更多的事情以解决这个问题。 再次感谢您的帮助和建议。 问候 戴夫 以上来自于谷歌翻译 以下为原文 Hi Austin Accepted. Its just that this one board behaves so differently to the rest, but that said it was built around 1 year ago and the Lot code of the device is different to the other 10 boards we have, all of which have the same Lot code. It is 10PM in th evenng in the UK so I will implement your suggestion tomorrow when I get to the office. There are other devices on the board that may not be so tollerant of the higher temperature, I will check. I was hoping for a quick way to prove that this was just a faulty device (or not) but it looks like I am going to have to do a lot more to bottom this problem out. Again thanks for your help and suggestions. regards Dave |
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戴夫,
由于过去几年的出货质量远低于百万分之十,因此一台设备坏的可能性几乎是百万分之一(因为我们运送了数百万)。 并且,是的,不同的批号将略有不同,因为该过程从未,现在不是完美的(速度可能因nmos,pmos或两者而异,并且仍然符合规格)。 为了运输零件,我们测试每个模具和每个包装零件,以确保它符合规格。 Austin Lesea主要工程师Xilinx San Jose 以上来自于谷歌翻译 以下为原文 Dave,With the shipped quality for the last few years being well below 10 parts per million, the chance that that one device is bad is literally one in a million (as we ship many millions).And, yes, a different lot number will be slightly different, as the process was never, and is not now, perfect (the speed may vary on nmos, pmos, or both, and still meet the specifications). In order to ship parts, we test every die, and every packaged part, to see that it meets the specifications.Austin Lesea Principal Engineer Xilinx San Jose |
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这对我来说确实听起来像是在你没有约束的路径上的时间违规。
----------------------------是的,我这样做是为了谋生。 以上来自于谷歌翻译 以下为原文 This really does sound to me like it's a timing violation on a path that you'd not constrained. ----------------------------Yes, I do this for a living. |
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