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嗨我正在使用Spartan-6 FPGA集成端点模块v1.3用于PCI Express。
我想从100 MHz差分clk派生出60 MHz。附上RTL视图解释了这个场景。 我收到以下错误。 错误：Pack：1107 - Pack无法将下面列出的符号组合到单个IPAD组件中，因为所选的站点类型不兼容。 进一步说明：符号CLK_GEN / clkin1_buf / SLAVEBUF.DIFFIN不是一种可以加入IPAD组件的符号。 涉及的符号：PAD符号“sys_clk_n”（填充信号= sys_clk_n）SlaveBuffer符号“CLK_GEN / clkin1_buf / SLAVEBUF.DIFFIN”（输出信号= CLK_GEN / clkin1_buf / SLAVEBUF.DIFFIN）BUF符号“refclk_ibuf_ML_IBUF2”（输出信号= refclk_ibuf_ML_IBUF2） 错误：Pack：1107 - Pack无法将下面列出的符号组合到单个IPAD组件中，因为所选的站点类型不兼容。 进一步说明：符号CLK_GEN / clkin1_buf / IBUFDS不是一种可以加入IPAD组件的符号。 涉及的符号：PAD符号“sys_clk_p”（填充信号= sys_clk_p）DIFFAMP符号“CLK_GEN / clkin1_buf / IBUFDS”（输出信号= CLK_GEN / clkin1）BUF符号“refclk_ibuf_ML_IBUF1”（输出信号= refclk_ibuf_ML_IBUF1） 请提出解决方案。 提前致谢 卡皮尔 以上来自于谷歌翻译 以下为原文 Hi I am using Spartan-6 FPGA Intergrated Endpoint Block v1.3 for PCI Express. I want to derive 60 MHz from 100 MHz differential clk.. Attached is RTL view explaning the scenario. and I am getting the following error. ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a single IPAD component because the site type selected is not compatible. Further explanation: Symbol CLK_GEN/clkin1_buf/SLAVEBUF.DIFFIN is not a kind of symbol that can join an IPAD component. Symbols involved: PAD symbol "sys_clk_n" (Pad Signal = sys_clk_n) SlaveBuffer symbol "CLK_GEN/clkin1_buf/SLAVEBUF.DIFFIN" (Output Signal = CLK_GEN/clkin1_buf/SLAVEBUF.DIFFIN) BUF symbol "refclk_ibuf_ML_IBUF2" (Output Signal = refclk_ibuf_ML_IBUF2) ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a single IPAD component because the site type selected is not compatible. Further explanation: Symbol CLK_GEN/clkin1_buf/IBUFDS is not a kind of symbol that can join an IPAD component. Symbols involved: PAD symbol "sys_clk_p" (Pad Signal = sys_clk_p) DIFFAMP symbol "CLK_GEN/clkin1_buf/IBUFDS" (Output Signal = CLK_GEN/clkin1) BUF symbol "refclk_ibuf_ML_IBUF1" (Output Signal = refclk_ibuf_ML_IBUF1) Please suggest a solution. Thanks in advance Kapil 
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10个回答
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嗨，
出现此错误的原因有很多，通常在IOB未正确锁定时会出现。 所需细节： 1.ISE / PlanAhead版本？ 2.Spartan 6设备部分？ 3.IO引脚锁定细节 您能否查看下面的详细信息？1。如果IO焊盘所在的bank支持与引脚相关的IO标准。如果IO焊盘锁定与GT时钟有关，因为它们不能用于通用 如果IO锁定是1：1完成的，即n到n，p到p 问候， Achutha -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- -------------- 以上来自于谷歌翻译 以下为原文 Hi , This error occurs for many reasons, commonly seen when the IOBs are not locked correctly. Details required: 1.ISE/PlanAhead version? 2.Spartan 6 device part? 3.IO pins locking details Can you please check the below details? 1.If the bank where the IO pads are located supports the IO standard associated to the pins. 2.if the IO pads locked are related to GT clocks as they can't be used for general purpose 3.if IO locking is done 1:1, i.e. n to n and p to p Regards, Achutha --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------- |
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从您共享的技术原理图快照中，我可以发现问题。
来自输入板的信号可以直接驱动资源（CLK_GEN），也可以驱动驻留在IOB块中的缓冲区（refclk_ibuf）。 在您的情况下，您正在驱动输入焊盘信号sys_clk_p＆amp; sys_clk_n到输入缓冲区和结构。 这不是一个法律结构。 请修改它以解决错误。 -------------------------------------------------- ---------------------------------------------请将帖子标记为 如果提供的信息能够回答您的问题/解决您的问题，请“接受为解决方案”。给予您认为有用的帖子。 以上来自于谷歌翻译 以下为原文 From the technology schematic snapshot that you shared, I could spot an issue. The signal from input pad can either drive a resource (CLK_GEN) directly or it can drive a buffer (refclk_ibuf) that resides in IOB tile. In your case, you are driving the input pad signals sys_clk_p & sys_clk_n to both input buffer and the fabric. This is not a legal structure. Please modify it to resolve the error. ----------------------------------------------------------------------------------------------- Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue. Give Kudos to a post which you think is helpful. |
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HI Smarell，
谢谢你快速的回复。 你对这种情况有什么修改建议，我的要求是我必须从100MHz差分clk驱动60MHz（来自CLK_GEN）clk，同样的差分clk驱动PCIe核心。 问候 卡皮尔 以上来自于谷歌翻译 以下为原文 HI Smarell, Thanks for your quick response. What modification do u suggest for this scenario, my requirment is I have to derive the 60MHz (from CLK_GEN) clk from the 100MHz differential clk and the same differential clk drive the PCIe core. Regards Kapil |
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你可以试试Map -ignore_keep_hierarchy可以解决这个问题，还是XST -keep_hierarchy软？
以上来自于谷歌翻译 以下为原文 Can you try with Map -ignore_keep_hierarchy can workaround this issue, or XST -keep_hierarchy soft? |
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您可以考虑使用ibuds输出驱动CLK_GEN输入并获得60 MHz时钟。
-------------------------------------------------- ---------------------------------------------请将帖子标记为 如果提供的信息能够回答您的问题/解决您的问题，请“接受为解决方案”。给予您认为有用的帖子。 以上来自于谷歌翻译 以下为原文 You can consider driving CLK_GEN input with the ibuds output and derive the 60 MHz clock.----------------------------------------------------------------------------------------------- Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue. Give Kudos to a post which you think is helpful. |
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嗨Achutha，
感谢您的快速回复，以下是详细信息： 所需细节： 1.ISE / PlanAhead版本？ 12.1 2.Spartan 6设备部分？ 12.1 3.IO引脚锁定细节 NET sys_clk_n LOC = B10; NET sys_clk_p LOC = A10; 您能否查看以下详细信息？1。如果IO焊盘所在的bank支持与引脚相关的IO标准。 是2.如果IO垫锁定与GT时钟有关，因为它们不能用于通用目的 MGTREFCLK0N_101 MGTREFCLK0P_101 如果IO锁定是1：1完成的，即n到n，p到p 问候 卡皮尔。 以上来自于谷歌翻译 以下为原文 Hi Achutha, Thanks for your quick response, following are the details: Details required: 1.ISE/PlanAhead version? 12.1 2.Spartan 6 device part? 12.1 3.IO pins locking details NET sys_clk_n LOC = B10; NET sys_clk_p LOC = A10; Can you please check the below details? 1.If the bank where the IO pads are located supports the IO standard associated to the pins. Yes 2.if the IO pads locked are related to GT clocks as they can't be used for general purpose MGTREFCLK0N_101 MGTREFCLK0P_101 3.if IO locking is done 1:1, i.e. n to n and p to p regards Kapil. |
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嗨Smarell，
试过这个，但得到以下错误： 错误：LIT：544 - BUFDS符号“physical_group_sys_clk_c / refclk_ibuf_ML_BUFDS”（输出信号= sys_clk_c）只能驱动GTPA1_DUAL的CLK00，CLK01，CLK10或CLK11引脚。 请修改设计以避免不可故障的情况。逻辑drc期间发现错误。 问候 卡皮尔 以上来自于谷歌翻译 以下为原文 Hi Smarell, Tried this too, but got the following error: ERROR:LIT:544 - BUFDS symbol "physical_group_sys_clk_c/refclk_ibuf_ML_BUFDS" (output signal=sys_clk_c) can only drive a GTPA1_DUAL's CLK00, CLK01, CLK10, or CLK11 pins. Please modify the design to avoid an unroutable situation. Errors found during logical drc. Regards Kapil |
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嗨Siktap，
试过这个，得到了以下错误。 错误：Pack：1107 - Pack无法将下面列出的符号组合到单个IPAD组件中，因为所选的站点类型不兼容。 进一步说明：符号CLK_GEN / clkin1_buf / SLAVEBUF.DIFFIN不是一种可以加入IPAD组件的符号。 涉及的符号：PAD符号“sys_clk_n”（填充信号= sys_clk_n）SlaveBuffer符号“CLK_GEN / clkin1_buf / SLAVEBUF.DIFFIN”（输出信号= CLK_GEN / clkin1_buf / SLAVEBUF.DIFFIN）BUF符号“refclk_ibuf_ML_IBUF2”（输出信号= refclk_ibuf_ML_IBUF2） 错误：Pack：1107 - Pack无法将下面列出的符号组合到单个IPAD组件中，因为所选的站点类型不兼容。 进一步说明：符号CLK_GEN / clkin1_buf / IBUFDS不是一种可以加入IPAD组件的符号。 涉及的符号：PAD符号“sys_clk_p”（填充信号= sys_clk_p）DIFFAMP符号“CLK_GEN / clkin1_buf / IBUFDS”（输出信号= CLK_GEN / clkin1）BUF符号“refclk_ibuf_ML_IBUF1”（输出信号= refclk_ibuf_ML_IBUF1） 问候 卡皮尔。 以上来自于谷歌翻译 以下为原文 Hi Siktap, Tried this on too, got following error. ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a single IPAD component because the site type selected is not compatible. Further explanation: Symbol CLK_GEN/clkin1_buf/SLAVEBUF.DIFFIN is not a kind of symbol that can join an IPAD component. Symbols involved: PAD symbol "sys_clk_n" (Pad Signal = sys_clk_n) SlaveBuffer symbol "CLK_GEN/clkin1_buf/SLAVEBUF.DIFFIN" (Output Signal = CLK_GEN/clkin1_buf/SLAVEBUF.DIFFIN) BUF symbol "refclk_ibuf_ML_IBUF2" (Output Signal = refclk_ibuf_ML_IBUF2) ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a single IPAD component because the site type selected is not compatible. Further explanation: Symbol CLK_GEN/clkin1_buf/IBUFDS is not a kind of symbol that can join an IPAD component. Symbols involved: PAD symbol "sys_clk_p" (Pad Signal = sys_clk_p) DIFFAMP symbol "CLK_GEN/clkin1_buf/IBUFDS" (Output Signal = CLK_GEN/clkin1) BUF symbol "refclk_ibuf_ML_IBUF1" (Output Signal = refclk_ibuf_ML_IBUF1) Regards Kapil. |
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使用spartan-6 GTP时，GTP的REFCLK输入不能用作结构的时钟输入。
请为此输入选择正常的IO引脚。 -------------------------------------------------- ----------------------------别忘了回复，给予kudo并接受为解决方案--------- -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 With spartan-6 GTP, the REFCLK input to GTP cannot be used as a clock input to fabric. Please select a normal IO pin for this input.------------------------------------------------------------------------------ Don't forget to reply, give kudo and accept as solution ------------------------------------------------------------------------------ |
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