发 帖  
原厂入驻New
[问答]

SPARTAN6到ZYNQ PRIMITIVES CONVERSION不匹配

644 xilinx Zynq spartan6
分享
嗨,
我有一些问题,比如一些斯巴达原语与zynq设备不匹配。
你能告诉我如何转换
斯巴达BUFIO2,BUFPLL,Iserdes,IODELAY对ZYNQ设备原语的描述。

以上来自于谷歌翻译


以下为原文

Hi,
   I have few problems like some of the spartan primitives are not matching with zynq devices. Cn you please tell me how to convert
   spartan BUFIO2, BUFPLL, ISERDES, IODELAY primitives  to ZYNQ Device primitives.
0
2019-4-9 13:27:52   评论 分享淘帖 邀请回答

相关问题

2个回答
本指南可能会对您有所帮助:http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/ug911-vivado-migration.pdf
谢谢和RegardsBalkrishan -----------------------------------------------
---------------------------------------------请将帖子标记为
一个答案“接受为解决方案”,以防它有助于解决您的查询。如果一个帖子引导到解决方案,请给予赞誉。

以上来自于谷歌翻译


以下为原文

this guide may help you

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/ug911-vivado-migration.pdfThanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
2019-4-9 13:38:32 评论

举报

简而言之,您无法自动或机械地执行此操作。
Spartan-6和7系列器件(尤其是Zynq)的时钟结构(特别是)非常不同。
您必须重新审视所有I / O接口的设计,并使用7系列结构重新设计它们。
对于某些事情,这将是相当简单的,对于其他人,它将需要回到绘图板并找出你需要的东西,然后为Zynq设计一个新的结构。
具体来说,BUFIO2没有直接转换。
通常使用BUFIO和BUFR可以实现相同的目的,但并非总是如此,因为BUFR不是全局缓冲区(而BUFIO2的DIVCLK输出上使用的BUFG是全局的),因此您的架构可能需要修改。
类似地,没有相当于BUFPLL  - 在某些应用中可以使用BUFG,在其他应用中可以使用BUFIO / BUFR组合。
ISERDES在两个设备中非常相似,但时钟要求非常不同(实际上就是上述所有内容)。
Spartan-6中的IODELAY与7系列中的IDELAY / ODELAY截然不同。
7系列是通过PVT校准的,而Spartan-6则不是。
但是,S6 IODELAY(相位检测器)的一个特点是在7系列中没有直接模拟。
Avrum

以上来自于谷歌翻译


以下为原文

In a nutshell, you can't do this automatically or mechanically.
 
The clocking structure (in particular) of a Spartan-6 and a 7 series device (which is what Zynq is) are really quite different. You have to revisit the design of all your I/O interfaces and re-design them using 7 series structures.
 
For some things, this will be fairly simple, for others it will require going back to the drawing board and figuring out what you need and then designing a new structure for the Zynq.
 
Specifically, there is no direct conversion for the BUFIO2. Generally the same thing can be accomplished with a BUFIO and a BUFR, but not always, since the BUFR is not a global buffer (whereas the BUFG used on the DIVCLK output of the BUFIO2 is global) so your architecture may need to be modifed. Similarly, there is no equivalent to the BUFPLL - in some applications a BUFG can be used, in others a BUFIO/BUFR combination.
 
The ISERDES is pretty similar in the two devices, but the clocking requirements are pretty different (really that's what all the above stuff is about).
 
The IODELAY in the Spartan-6 is pretty different than the IDELAY/ODELAY in the 7 series. The 7 series is calibrated over PVT, whereas the Spartan-6 one isn't. But, there is a feature of the S6 IODELAY (the phase detector) that has no direct analogue in the 7 series.
 
Avrum
2019-4-9 13:56:55 评论

举报

只有小组成员才能发言,加入小组>>

153个成员聚集在这个小组

加入小组

创建小组步骤

快速回复 返回顶部 返回列表