请问我是否能获得ODDR2的Q（输出）的反馈线并将异步输出到另一个引脚？

我认为你在帖子中交换了IOBUF的O和I引脚。
O引脚是输入缓冲器的输出。
即，它是IOBUF原语的输出，而不是输出到焊盘的连接。
类似地，I引脚是输出缓冲器的输入，并且将从ODDR2获取PWM数据。
-  Gabor
在原帖中查看解决方案



以下为原文

I think you have the O and I pins of the IOBUF swapped in your post.  The O pins is the output of the input buffer.  i.e. it is an output of the IOBUF primitive and not the connection for output to the pad.  Similarly the I pin is the input of the output buffer, and would take your PWM data from the ODDR2.
-- GaborView solution in original post

您可以在ODDR2之后使用IOBUF来获得引脚反馈，但问题是为什么不在另一个引脚上复制ODDR2？
ODDR2_2：ODDR2通用映射（DDR_ALIGNMENT =>“NONE”， - 将输出对齐设置为“NONE”，“C0”，“C1”INIT =>'0'， - 将Q输出的初始状态设置为“0”
或'1'SRTYPE =>“SYNC”） - 指定“SYNC”或“ASYNC”设置/复位端口映射（Q => pwm_2， -  1位输出数据C0 => clk2x， -  1位时钟
输入C1 => clk180， -  1位时钟输入CE =>'1'， -  1位时钟使能输入D0 => d1_oddr_1， -  1位数据输入（与C0相关）D1 => d2_oddr_1，
-  1位数据输入（与C1相关）R =>'0'， -  1位复位输入S =>'0' -  1位置位输入）;
-  Gabor



以下为原文

You can use an IOBUF after the ODDR2 to get pin feedback, but the question I have is why not just replicate the ODDR2 at the other pin?
 
ODDR2_2 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => pwm_2, -- 1-bit output data
C0 => clk2x, -- 1-bit clock input
C1 => clk180, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => d1_oddr_1, -- 1-bit data input (associated with C0)
D1 => d2_oddr_1, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
-- Gabor

的Gabor，
有趣的是在ODDR2之后使用IOBUF。
要回答关于我为什么要这样做的问题是一个很好的问题。
我们正在为需要“SIL-4”级安全性的客户开展项目。
如果我们添加两个单独的ODDR2，从安全角度来看可能意味着ODDR 1工作不正常并且我们正在监视的ODDR 2正常工作。
因此，我们不会检测到我们的PWM输出没有按预期工作，并且当设备应该“关闭”时，我们可以调制不需要的信号。
因此，为了取悦安全人员，我们希望直接从引脚反馈并将其路由到另一个FPGA进行监控，这将为我们提供所需的PWM信号可观察性。
如果这不起作用（或安全人员不喜欢它），我们必须重新设计我们的PCB并设计并在FPGA外部将导线布线到外部，这将是我们项目完成的一大延迟。
显然，安全人员正在挑选一个非常不可能的事件，它会让你拉出你的头发。



以下为原文

Gabor,
 
Interesting about using IOBUF after the ODDR2.  
 
To answer the question about why I would want to do this is a good one.
 
We are doing a project for a customer that demands a "SIL-4" level of safety.  If we add two seperate ODDR2 that from a safety perspective could mean that ODDR 1 is working incorrectly and the ODDR 2 that we are monitoring is working correctly.  Therefore we would not detect that our PWM output is not working as intended and we could modulate a unwanted signal when the device is supposed to be "OFF".  
 
So to please the safety guys we are hoping that feedback straight off the pin and routing it to another FPGA to monitor will give us the needed observability of the PWM signal.  
 
If this doesn't work (or the safety guys don't like it) we have to respin our PCB and design and route the wires externally outside the FPGA which will be a big delay in our project completion.
 
Obviously the safety guys are nit picking at an event that is so improbable that it makes you pull out your hair.
 
 
 

那么如何实例化IOBUF :(有没有关于对输出引脚做反馈的文档？）
顶级引脚将采用VHDL：
PWM_1：inout std_logic;
ODDR2_1：ODDR2通用映射（DDR_ALIGNMENT =>“NONE”， - 将输出对齐设置为“NONE”，“C0”，“C1”INIT =>'0'， - 将Q输出的初始状态设置为“0”
或'1'SRTYPE =>“SYNC”） - 指定“SYNC”或“ASYNC”设置/复位端口映射（Q => pwm_1_OUTPUT， -  1位输出数据C0 => clk2x， -  1位时钟
输入C1 => clk180， -  1位时钟输入CE =>'1'， -  1位时钟使能输入D0 => d1_oddr_1， -  1位数据输入（与C0相关）D1 => d2_oddr_1，
-  1位数据输入（与C1相关）R =>'0'， -  1位复位输入S =>'0' -  1位置位输入）; 
IOBUF_inst：IOBUF通用映射（DRIVE => 12，IBUF_DELAY_VALUE =>“0”， - 指定缓冲区添加的输入延迟量， - “0” - “16”IFD_DELAY_VALUE =>“AUTO”， - 指定
输入寄存器增加的延迟量， - “AUTO”，“0” - “8”IOSTANDARD =>“DEFAULT”，SLEW =>“SLOW”）端口映射（O => pwm_1_OUTPUT， - 缓冲输出IO =>
pwm_1， - 缓冲输入端口（直接连接到顶级端口）I => PWM_TO_OTHER_FPGA， - 缓冲输入T => T  -  3状态使能输入，高=输入，低=输出）;
-  IOBUF_inst实例化结束
谢谢
C



以下为原文

So how do you instantiate the IOBUF:  (Is there any documentation about doing feedback on output pins?)
 
TOP level the pin would be in VHDL:
 
PWM_1 : inout  std_logic ;
 
ODDR2_1 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => pwm_1_OUTPUT, -- 1-bit output data
C0 => clk2x, -- 1-bit clock input
C1 => clk180, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => d1_oddr_1, -- 1-bit data input (associated with C0)
D1 => d2_oddr_1, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
 
 

IOBUF_inst : IOBUF
generic map (
DRIVE => 12,
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
-- "0"-"16"
IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register,
-- "AUTO", "0"-"8"
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => pwm_1_OUTPUT, -- Buffer output
IO => pwm_1, -- Buffer inout port (connect directly to top-level port)
I => PWM_TO_OTHER_FPGA, -- Buffer input
T => T -- 3-state enable input, high=input, low=output
);

-- End of IOBUF_inst instantiation
 
Thanks
 
C

我认为你在帖子中交换了IOBUF的O和I引脚。
O引脚是输入缓冲器的输出。
即，它是IOBUF原语的输出，而不是输出到焊盘的连接。
类似地，I引脚是输出缓冲器的输入，并且将从ODDR2获取PWM数据。
-  Gabor



以下为原文

I think you have the O and I pins of the IOBUF swapped in your post.  The O pins is the output of the input buffer.  i.e. it is an output of the IOBUF primitive and not the connection for output to the pad.  Similarly the I pin is the input of the output buffer, and would take your PWM data from the ODDR2.
-- Gabor

是的，你是对的。
谢谢您的帮助！
C



以下为原文

Yes you are correct.  
 
Thanks for the help!
 
C

这是为其他人想知道如何做到这一点：
顶级引脚将采用VHDL：
PWM_1：inout std_logic;
PWM_1_out_to_other_fpga：out std_logic;
ODDR2_1：ODDR2generic map（DDR_ALIGNMENT =>“NONE”， - 将输出对齐设置为“NONE”，“C0”，“C1”INIT =>'0'， - 将Q输出的初始状态设置为“0”或
'1'SRTYPE =>“SYNC”） - 指定“SYNC”或“ASYNC”设置/重置端口映射（Q => pwm_1_OUTPUT， -  1位输出dataC0 => clk2x， -  1位时钟inputC1 =>
clk180， -  1位时钟输入CE =>'1'， -  1位时钟使能inputD0 => d1_oddr_1， -  1位数据输入（与C0相关）D1 => d2_oddr_1， -  1位数据
输入（与C1相关）R =>'0'， -  1位复位输入S =>'0' -  1位置位输入）;
IOBUF_inst：IOBUFgeneric map（DRIVE => 12，IBUF_DELAY_VALUE =>“0”， - 指定缓冲区添加的输入延迟量， - “0” - “16”IFD_DELAY_VALUE =>“AUTO”， - 指定金额
延迟输入寄存器， - “AUTO”，“0” - “8”IOSTANDARD =>“DEFAULT”，SLEW =>“SLOW”）端口映射（O => PWM_TO_OTHER_FPGA， - 缓冲器outputIO => pwm_1，
- 缓冲输入端口（直接连接到顶级端口）I => pwm_1_OUTPUT， - 缓冲输入T =>'0' -  3状态使能输入，高=输入，低=输出）;
PWM_1_out_to_other_fpga PWM_TO_OTHER_FPGA;



以下为原文

This is how to do it for anyone else wondering:
 
 
 
TOP level the pin would be in VHDL:
 
PWM_1 : inout  std_logic ;
 
PWM_1_out_to_other_fpga : out std_logic;
 
ODDR2_1 : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => pwm_1_OUTPUT, -- 1-bit output data
C0 => clk2x, -- 1-bit clock input
C1 => clk180, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => d1_oddr_1, -- 1-bit data input (associated with C0)
D1 => d2_oddr_1, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
 
 

IOBUF_inst : IOBUF
generic map (
DRIVE => 12,
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, 
-- "0"-"16" 
IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, 
-- "AUTO", "0"-"8" 
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => PWM_TO_OTHER_FPGA, -- Buffer output
IO => pwm_1, -- Buffer inout port (connect directly to top-level port)
I => pwm_1_OUTPUT, -- Buffer input
T => '0' -- 3-state enable input, high=input, low=output 
);
 
 
PWM_1_out_to_other_fpga  <= PWM_TO_OTHER_FPGA;

csholikowski写道：
ODDR2_1：ODDR2 
端口映射（Q => pwm_1， -  1位输出数据C0 => clk2x， -  1位时钟输入C1 => clk180， -  1位时钟输入CE =>'1'， -  1-
位时钟使能输入D0 => d1_oddr_1， -  1位数据输入（与C0相关）D1 => d2_oddr_1， -  1位数据输入（与C1相关）R =>'0'， -  1位
复位输入S =>'0' -  1位置位输入）;
当然你想让C1成为CLK2X180，对吧？
----------------------------是的，我这样做是为了谋生。



以下为原文

csholikowski wrote:
 
ODDR2_1 : ODDR2
port map (
Q => pwm_1, -- 1-bit output data
C0 => clk2x, -- 1-bit clock input
C1 => clk180, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => d1_oddr_1, -- 1-bit data input (associated with C0)
D1 => d2_oddr_1, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);

Surely you want C1 to be CLK2X180, right?
----------------------------Yes, I do this for a living.