DDR LVDS设计端口为Spartan 6无法工作

我目前正致力于将设计从Spartan 3（XC3S200-VQ100 -5速度等级）移植到更新的Spartan 6 XC6SLX-100-2CSG484。
所有斯巴达3都做了吐出从块ram到DDR LVDS25输出的数据saplems驱动高速DAC（这在spartan 3上达到220MHz DDR（440兆样本/秒）就好了）。
它还做了一些其他基本的系统设置，比如通过SPI编程PLL，但总体上没什么用。
当我尝试使用较新的IO对象即时插件将此设计移植到Spartan 6时，它将无法工作。
设计将会实现，但即使针对Spartan 6的更快的-3版本，它总是会失去时序约束（适用于220MHz DDR）。当我看到布局和布局后的路由时，它似乎只是简单地路由信号来自
以非常愚蠢的方式阻止ram到DDR输出寄存器。
我在数据信号路径中使用寄存器流水线以允许高速在芯片上进行路由（静态延迟时间不会影响此应用）。
它似乎将这些信号组合在一起直到ODDR2之前，并且它试图跳过整个芯片并且那时定时失败（当我需要少于4.545ns时，路径延迟高达10或12 ns）。
有没有人有这样的设计经验（块Lm的DDR LVDS 220MHz数据输出）？
我只是傻眼了，因为它在更老的Spartan 3上运行得很好，从那以后技术已经走了很长的路。
如果您需要更多说明，我可以在回复中提供。
为了清楚起见，我已将输出全部限制为Bank 0 vaild LVDS对。
另外作为参考，我正在使用Vertex-4的项目中使用类似的设计也可以正常工作。
编辑：
只是为了加快一些事情
这是斯巴达3设计的想法
（注意银行a为0阶段，银行b为180阶段）
双端口滑块 - > FDDRCPE  - > OBUFDS  - >物理焊盘
由于斯巴达6上可用的灵长类动物的变化，这是我当前的设置不起作用
（注意除了ODDR2为C1提供180相时钟之外，所有在0阶段都处于中断状态）
两个块rams  - >注册管道 - >（！！定时错误！） - > ODDR2  - > OBUFDS  - >物理垫
我在移植时更多地参考了我们的顶点4设计，并且使用了ODDR原型，因此我认为ODDR2可以正常工作。
它似乎没有抱怨ODDR2具有内置OBUF，我认为可能是一个问题。
提前致谢，
〜马特
消息由calvinmc于01-25-2010 02:09 PM编辑



以下为原文

I am currently working on porting a design from a Spartan 3 (XC3S200-VQ100 -5 speed grade) to a newer Spartan 6 XC6SLX-100-2CSG484.  All the spartan 3 did was spit out data saplems from block ram to DDR LVDS25 outputs to drive a high speed DAC (this worked up to 220MHz DDR (440 mega samples/sec) on the spartan 3 just fine).  It also did some other basic system setup like programming of PLLs over SPI but nothing much overall.  When I try to port this design to the Spartan 6 using the newer IO object instantitaions and the such it will not work.  The design will implment but it always fails timing constraints (going for 220MHz DDR) even when targeting the faster -3 version of the Spartan 6.  When I look at the layout and routing after implmentation it seems that it is simply routing the signals from the block ram to the DDR output registers in a very silly way.  I use a register pipeline in my data signal paths to allow for routing across the chip at high speeds (static delay times don't hurt this application).  It seems to keep these signals grouped together right up until before the ODDR2s and the it tries to jump all over the chip and thats where the timing fails (up to 10 or 12 ns of path delay when I need less then 4.545ns).  Does anyone have any experience doing a design like this (DDR LVDS 220MHz data output from block ram)?  I'm just dumbfounded as it works great on the much older Spartan 3 and the technology has come a long way since then.  If you need any more clarificaion I can provide in a reply.  Just to be clear I have constrained my outputs all to Bank 0 vaild LVDS pairs. Also for reference, a similar design is currently used on the project I'm on with a Vertex-4 that also works just fine.

edit:
Just to califiy some things
this is the idea of the spartan 3 design
(note bank a at 0 phase, bank b at 180 phase)
Dual port block ram -> FDDRCPE -> OBUFDS ->physical pads

Due to changes in the avaliable primatives on the spartan 6 this is my current setup that doesn't work
(note everything cloked at 0 phase except the ODDR2 is fed a 180 phase clock for C1)
Two block rams -> register pipeline -> (!timing error here!) -> ODDR2 -> OBUFDS ->physical pads
I referenced our vertex 4 design more when porting and in that ODDR primatives were used so I assue the ODDR2 would work fine.  It doesn't seem to be complaing about the ODDR2 primative having a built in OBUF which I thought might be a problem.

Thanks in advance,
~Matt
Message Edited by calvinmc on  01-25-2010 02:09 PM