CPU/FPGA接口是1.8V，如果将VCCO_2连接到1.8V，FPGA能否正确配置？

嗨，
我的系统主要运行在3.3V，但来自CPU的32位EMI（外部存储器接口）为1.8V＆amp;
3.3V。
我知道，这有点奇怪，但不幸的是，当我需要使用32位时，这就是CPU的情况。
BUS [31:16]为3.3V，BUS [15：0]为1.8V。
时钟，OE_N，WE_N信号也是1.8V。
我在主串行模式下使用Spartan 3E。
CPU负责使用该模式配置FPGA。
我有几个问题：
1.因为，CPU / FPGA接口是1.8V，如果我将VCCO_2连接到1.8V，FPGA能否正确配置？
此时，FPGA仍为空白，因此不知道每个引脚分配了什么IOSTANDARD。
2.成功配置后（每个引脚知道IOSTANDARD后），FPGA时钟源也来自CPU（同步）和@ 1.8V。
但其余的IO银行都在3.3V。
如何在FPGA内部工作？
在FPGA内部，它是一个通用逻辑'1'（如果它是1.8V或3.3V无关紧要）？
我不确定我是否清楚地解释了我的担忧。
但是，如果时钟源与1.8V的触发器的电压为1.8V，则75％的使用触发器为3.3V（只有VCCO_2为1.8V，其余的IO组为3.3V），那么
FPGA内的任何电压阈值问题??
谢谢...



以下为原文

Hi,

my system is mostly running on 3.3V,but the 32-bit EMI (external memory interfac) from the CPU is at 1.8V & 3.3V. I know, it's kinda weird, but unfortunately, that's how it is with the CPU when I need to use 32-bit. BUS[31:16] is on 3.3V, and BUS[15:0] is on 1.8V. the clock, OE_N, WE_N signals are also on 1.8V.

I'm using Spartan 3E on Master Serial Mode. the CPU is responsible to configure the FPGA using that mode.

I have a few questions:

1. because, the CPU/FPGA interface is 1.8V, if I tie VCCO_2 to 1.8V, will the FPGA be able to be configured correctly?
At this point in time, FPGA is still blank, so it doesn't know what IOSTANDARD is assigned for each pin.

2. after successful config (after each pin knows the IOSTANDARD), the FPGA clock source is also coming from CPU (synchronous) and @ 1.8V.
but the rest of the IO banks are on 3.3V. how is that gonna work, internally to the FPGA?
inside the FPGA, is it a universal logic '1' (doesn't matter if it's 1.8V or 3.3V)?
i'm not sure if I'm explaining my concern clearly.
but, if the clock source is at 1.8V to the flops at 1.8V, then 75% of the used flops are on 3.3V (only VCCO_2 is at 1.8V, the rest of the IO banks are on 3.3V), will there any voltage threshold problem inside the FPGA??

thanks...