Xilinx Virtex 5 FPGA可以接受逻辑电平0/1.8V的输入吗

是。
您还没有告诉我们您尝试使用的I / O标准 - 有多种不同的标准（LVCMOS，HSTL，SSTL和一大堆差分标准）。
我假设你在谈论LVCMOS。
但是，I / O的电压电平由BANK的VCCO决定。
因此，要使用LVCMOS18输入，该存储区的VCCO必须为1.8V，并且要驱动LVCMOS33输出，该存储区的VCCO必须为3.3V。
因此，您不能在同一个存储区中输入和输出（并且您的电路板必须设计为至少有一个1.8V存储区和一个3.3V存储区）。
一些其他I / O标准有不同的要求。
例如，SSTL18_I或HSTL_I_18输入不要求VCCO为1.8V，但要求VREF为0.9V。
虽然通常不会这样做，但您可能有一个VCCO = 3.3且VREF = 1.8的存储区，因此在同一存储区中有一个HSTL_I_18输入和一个LVCMOS33输出。
UG190第6章“选择I / O资源”，“在同一组中组合I / O标准的规则”一节中介绍了在银行中组合不同I / O标准的完整规则。
Avrum
在原帖中查看解决方案



以下为原文

Yes.
 
You haven't told us what I/O standards you are trying to use - there are multiple different standards (LVCMOS, HSTL, SSTL, and a whole bunch of differential ones). I will assume you are talking about LVCMOS.
 
However, the voltage level of an I/O is determined by the VCCO of the BANK. So, to use an LVCMOS18 input, the VCCO for the bank must be 1.8V, and to drive an LVCMOS33 output, the VCCO for the bank must be 3.3V. Therefore, you cannot have the input and output in the same bank (and your board has to be designed with at least one 1.8V bank and one 3.3V bank).
 
Some of the other I/O standards have different requirements. For example, an SSTL18_I or HSTL_I_18 input does not require VCCO to be 1.8V, but does require the VREF to be 0.9V. While not generally done, you could have a bank with VCCO=3.3 and VREF=1.8, and therefore have an HSTL_I_18 input and a LVCMOS33 output in the same bank.
 
The complete set of rules for combining different I/O standards in banks is shown in UG190, Chapter 6 "Select I/O Resources", section "Rules for Combining I/O Standards in the Same Bank".
 
Avrum
View solution in original post

是。
您还没有告诉我们您尝试使用的I / O标准 - 有多种不同的标准（LVCMOS，HSTL，SSTL和一大堆差分标准）。
我假设你在谈论LVCMOS。
但是，I / O的电压电平由BANK的VCCO决定。
因此，要使用LVCMOS18输入，该存储区的VCCO必须为1.8V，并且要驱动LVCMOS33输出，该存储区的VCCO必须为3.3V。
因此，您不能在同一个存储区中输入和输出（并且您的电路板必须设计为至少有一个1.8V存储区和一个3.3V存储区）。
一些其他I / O标准有不同的要求。
例如，SSTL18_I或HSTL_I_18输入不要求VCCO为1.8V，但要求VREF为0.9V。
虽然通常不会这样做，但您可能有一个VCCO = 3.3且VREF = 1.8的存储区，因此在同一存储区中有一个HSTL_I_18输入和一个LVCMOS33输出。
UG190第6章“选择I / O资源”，“在同一组中组合I / O标准的规则”一节中介绍了在银行中组合不同I / O标准的完整规则。
Avrum



以下为原文

Yes.
 
You haven't told us what I/O standards you are trying to use - there are multiple different standards (LVCMOS, HSTL, SSTL, and a whole bunch of differential ones). I will assume you are talking about LVCMOS.
 
However, the voltage level of an I/O is determined by the VCCO of the BANK. So, to use an LVCMOS18 input, the VCCO for the bank must be 1.8V, and to drive an LVCMOS33 output, the VCCO for the bank must be 3.3V. Therefore, you cannot have the input and output in the same bank (and your board has to be designed with at least one 1.8V bank and one 3.3V bank).
 
Some of the other I/O standards have different requirements. For example, an SSTL18_I or HSTL_I_18 input does not require VCCO to be 1.8V, but does require the VREF to be 0.9V. While not generally done, you could have a bank with VCCO=3.3 and VREF=1.8, and therefore have an HSTL_I_18 input and a LVCMOS33 output in the same bank.
 
The complete set of rules for combining different I/O standards in banks is shown in UG190, Chapter 6 "Select I/O Resources", section "Rules for Combining I/O Standards in the Same Bank".
 
Avrum

我需要通过bergsticks将ADC连接到FPGA。
Xilinx Virtex5 FPGA如何通过接头接受0和1.8V逻辑电平的外部输入？
我注意到Virtex5中的VCCIO = 2.5V或3.3V的XGI扩展头。
是否可以改变VCCIO电压？
或者是否有其他方式可以与FPGA连接？
任何帮助，将不胜感激。
谢谢。
asenapati



以下为原文

I need to interface an ADC to the FPGA through bergsticks. How can the Xilinx Virtex5 FPGA accept external input of logic levels 0 and 1.8V through headers?
I noticed that the VCCIO=2.5V or 3.3V of the XGI expansion headers in Virtex5. Is it possible to change the VCCIO voltage? or is there some other way in which i can interface to the FPGA?
 
Any help would be appreciated.
Thanks.
asenapati