如何约束时钟延迟树？

我帮你了，你的原理图看起来像这样：
或者你是如何实现缓冲系列的？
无论如何你已经读过这个缓冲区的符号信息了吗？
“这个元素不是必需的，并且被分区软件（MAP）删除。”
那么你是如何将“保持”属性应用于这些缓冲区以保护它们免受优化的影响呢？
我正在尝试类似的东西 - 通过可调延迟以每个500 ps的步长延迟几个信号。
目前我在试图让我的Spartan-3E的DCM工作时绝望。
也许这将是您移动信号的另一种选择。
当然这取决于你的输入时钟和你用过的芯片
来自德国的问候



以下为原文

Did I get you right, that your schematic looks something like this:
 
 
 Or how did u realize the series of buffers? 
Anyway have you already read the symbol info of this buffer parts? "This element is not necessary and is removed by the partitioning software (MAP)." So how did you applie the "keep" attribute to these buffers to protect them from beeing optimized away?
I'm trying something similar - to delay several signals by adjustable delay in steps of 500 ps each. At the moment I'm despairing while trying to get the DCM of my Spartan-3E to work. Maybe this would be another option for you to shift the signals.
Sure it depends on yout input clock and your used chip
 
Regards from Germany

我的设计与你的设计非常相似。
KEEP属性可以应用于BUF的网络，以便它们保留在您的设计中。
每个BUF都会产生类似的延迟时间，但BUF之间的路由延迟会有很大的不同，除非设计受到严格约束。
我昨天与某人讨论了一些实现更确定的延迟树的策略。
我今天要尝试一些实验，并发布我的结果。



以下为原文

My design is very similar to yours. The KEEP attribute can be applied to the nets of BUFs so that they will remain in your design. Each BUF will create a similar delay time, but the delay of the routing between BUFs will vary quite a bit unless the design is tightly constrained. I spoke with someone yesterday on some strategies to achieve a more deterministic delay tree. I am going to try some experiments today and will post my results.

这是我对Spartan II设计所做的简化版本。
1-为连接到BUFF的输入和输出的所有网络设置KEEP属性为TRUE，以使它们保持在设计中。
2-在UCF文件中，使用TPSYNC将时间组分配给链中的第一个缓冲区和链中的最后一个缓冲区（例如：INST“SYSC0”TPSYNC =“sysc0”; INST“SYSC6”TPSYNC =“sysc6”;）
。
如果您有多个分接头，则需要为每个分区指定一个时间组。
3-创建一个timespec以强制从链中的第一个缓冲区到最后一个缓冲区的最大延迟（例如：TIMESPEC“TS_1”= FROM“sysc0”TO“sysc6”8 ns;）。
如果您有多个水龙头，则需要约束每个部分。
当我使用缓冲区数量并强制工具限制时间时，我能够实现我所需要的...一个12抽头延迟树，在抽头之间有7ns +/- 1.5nS的延迟。
我的实际测量数字大约是我使用时序分析器看到的数字的0.8倍。



以下为原文

This is a simplified version of what I did with my Spartan II design.1- Set the KEEP attribute to TRUE for all nets connected to the input and output of the BUFFs to keep them in the design.2- In the UCF file, assign a timegroup using TPSYNC to the first buffer in the chain and the last buffer in the chain (example: INST "SYSC0" TPSYNC =  "sysc0"; INST "SYSC6" TPSYNC =  "sysc6";). If you have multiple taps, you will need to assign a timegroup to each section.3- Create a timespec to force the maximum delay from the first buffer to the last buffer in the chain (example: TIMESPEC "TS_1" = FROM "sysc0" TO "sysc6" 8 ns;). If you have multiple taps, you will need to constrain each section.When I played with the number of buffers and forced the tools to constrain the timing, I was able to acheive what I needed... a 12 tap delay tree with a 7ns +/-1.5nS delay between taps. My real world measured numbers were about 0.8x the numbers I saw using the timing analyzer.

我管理变量延迟类似于你描述它的方式。
对我来说，主要的问题是，如果我对其施加延迟，信号的脉冲宽度会发生变化。
任何sugesstions如何解决此错误？



以下为原文

Well I managed the variable delay similar to the way you described it.
The main problem for me is, that the signal varies in its pulswidths if I apply a delay to it.
Any sugesstions how to fix this error?

脉冲宽度变化多少？
你的时钟速度是多少？



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How much does the pulsewidth vary? What is your clock speed?

延迟可以500 ps的步长调节，输入时钟为13 MHz。
没有任何延迟，我输入50-50个时钟周期。
随着大约180-200°的变化，它看起来更像是35-65周期。



以下为原文

The delay is adjustable in steps of 500 ps with an input clock of 13 MHz.
Without any delay, I input an 50-50 clock cycle. With a shift of about 180-200° it looks more like a 35-65 cycle.