spartan 6时钟转发延迟问题

大家好
我是硕士论文的学生，我对FPGA编程没有太多经验，所以请耐心等待。
我正在使用Opal Kelly的XEM6010 spartan 6模块作为我的论文项目。
我所要做的就是在主机（FPGA）和从机（ADC）之间建立SPI通信，相对较低的频率为80MHz（带串行接口的1MSps ADC，实现最大采样率所需的80MHz时钟）
¯¯¯¯¯ _____ /¯¯¯¯¯ _____ /¯¯¯¯¯_____ /¯¯¯¯¯ _____ /¯¯¯¯¯¯ _____ / int_clk
¯¯¯¯¯ _________________________________________________ ser_start_end（master）
_____________________ /¯¯¯¯¯ _____ /¯¯¯¯¯ _____ /¯¯¯¯¯ _____ / ser_clk（master）
--------- XXXXXX
¯¯X¯¯¯¯Xser_adc_output（奴隶）
我必须得到上面描绘的内容。
所以基本上我必须将内部时钟输出到从器件，我还必须启用或禁用它（由于ADC的时序问题，这是必要的）。
我在这个论坛中发现，在spartan 6中转发时钟的最佳方法是使用ODDR2缓冲器，D0 = 1且D1 = 0 DDR_ALIGNMENT = 0来锁定时钟到输出，所以我做了。
我的内部时钟由外部PLL生成，由BUFG全局缓冲。
问题是，当我执行Post map时序分析时，我发现int_clk的上升沿和ser_clk之间存在很大的延迟（8.5ns）。
因为我需要80MHz时钟（12.5ns周期）8.5ns延迟不可接受。
ser_clk启用计时实际上不是问题购买我需要ser_clk不要与int_clk不同步。
我试图约束ser_clk，以便它从int_clk的延迟足够小
net“ser_clk”tnm_net =“ser_clk_out”; timegrp“ser_clk_out”offset =在“int_clk”上升后5 ns;
但那不行。
我获得的是静态时序报告称时序约束不受尊重。
我哪里错了？
感谢帮助



以下为原文

Hello everybody
I'm a master thesis student and I haven't got much experience on FPGA programming so please be patient with me.
I'm using XEM6010 spartan 6 module by Opal Kelly for my thesis project.
What I've got to do after all is just to set up SPI communication between master (FPGA) and slave (ADC), at the relatively low frequency of 80MHz (1MSps ADC with serial interface, 80MHz clock required to achieve maximum sampling rate)

¯¯¯¯¯_____/¯¯¯¯¯_____/¯¯¯¯¯_____/¯¯¯¯¯_____/¯¯¯¯¯_____/    int_clk
¯¯¯¯¯_________________________________________________    ser_start_end (master)
_____________________/¯¯¯¯¯_____/¯¯¯¯¯_____/¯¯¯¯¯_____/     ser_clk (master)
---------X¯¯¯¯¯¯¯¯¯¯¯¯¯¯X¯¯¯¯¯X¯¯¯¯X¯¯¯¯¯X¯¯¯¯X¯¯¯¯¯X¯¯¯¯X     ser_adc_output (slave)

I have to obtain what I've sketched above. So basically I have to take internal clock out to the slave and I also have to enable or disable it (that's necessary because of ADC's timing issues). I found in this forum that the best way to forward clock in spartan 6 is to use ODDR2 buffer with D0 = 1 and D1 = 0 DDR_ALIGNMENT = 0 to latch the clock to the output and so I did. My internal clock is generated by an external PLL, global buffered by BUFG.
The problem is that when I performed Post map timing analysis I found out a big delay (8.5ns) between  int_clk's rising edge and ser_clk's. As I need 80MHz clock (12.5ns period) 8.5ns delay's not accettable. ser_clk enable timing's actually's not an issue buy I need ser_clk not to be out of phase with int_clk.
I tryied to constraint ser_clk so that its delay from int_clk would be small enough

net "ser_clk" tnm_net = "ser_clk_out";
timegrp "ser_clk_out" offset = out 5 ns after "int_clk" rising;


but that's not work. What I gained was that static timing report said timing constraints were not respected.
Where am I wrong?
thanks for help