CLK可以从FPGA的I/O引脚进入吗？

是的，时钟可以来自输入（或I / O）引脚。
有没有与clk相关的问题？
我不明白这个问题。
你有特定的担忧或问题吗？
如果您担心警告消息或错误消息，则应发布整个消息和消息所解决的源代码。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

Yes, a clock can be sourced from an input (or I/O) pin.
 
Is there any clk related issue?
 
I don't understand this question.  Do you have a specific concern or problem?
 
If you are concerned about a warning message or error message, you should post the entire message and the source code which is addressed by the message.
 
-- Bob Elkind
 
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

有一段时间它会起作用。
之后它无法正常工作。
这非常模糊。
到底是什么“不工作？” 
构建 - 即您对设计进行了更改但却出错了？ 
硬件 - 即运行一段时间（比如10分钟）然后退出？ 
某些版本中的硬件 - 即您进行了更改而硬件不起作用？
如果FPGA外部没有任何东西使用相同的振荡器（即你没有
关心振荡器和进入的信号之间的相位关系
离开FPGA）然后你应该能够使用标准I / O引脚运行时钟。
由于非专用路由，可能会出现问题：
1）（构建到构建）路由延迟在构建之间可能有很大差异。
这影响了
振荡器输出和内部时钟之间的相位关系。
一般
这不是问题，除非你关心它之间的相对阶段
振荡器输出和其他外部信号。
2）（过程/温度/电压）非专用路由具有更长的延迟，并且
因此，即使PVT的百分比延迟变化与专用路线相同，
由于整体延迟较长，绝对延迟变化较大。
特别是在
在电压依赖的情况下，这可能会产生保持DCM锁定的问题。
构建到构建的更改可以增加或减少由于差异而产生的依赖性
在整体延迟。
-  Gabor
-  Gabor



以下为原文

 For some time it will work. after that it is not working.
 
This is extremely vague.  What exactly is "not working?"
 
  The build - i.e. you make a change to the design but get errors? 
 
  The hardware - i.e. it runs for a while (say 10 minutes) and then quits?
 
  The hardware on some builds - i.e. you make a change and the hardware doesn't work?
 
If there is nothing external to the FPGA that uses the same oscillator (i.e. you don't
care about the phase relationship between the oscillator and signals entering or
leaving the FPGA) then you should be able to run the clock using a standard I/O pin.
 
Problems can occur because of the non-dedicated routing:
 
1) (build to build) The routing delay can vary greatly between builds.  This affects the
phase relationship between the oscillator output and your internal clocks.  Normally
this is not a problem unless you do care about the relative phase between the
oscillator output and other external signals.
 
2) (Process / temperature / voltage) Non-dedicated routing has longer delays, and
thus even if the percentage delay change over PVT is the same as for dedicated routes,
the absolute delay changes more because of the overall longer delay.  Especially in
the case of voltage dependence, this can create problems keeping a DCM locked.
Build-to-build changes can increase or decrease the dependence due to differences
in the overall delay.
 
-- Gabor
-- Gabor

确实这是一个非常模糊的问题。
但是底线是他在IO引脚上使用clk输入时遇到的问题
我认为只要clk通过专用的bufg分布在芯片内部就可以了



以下为原文

Indeed it' s very vague question. but the bottom line he has an issue using clk input at an IO pin
 
I think it's ok as long as the clk is distributed inside the chip  with a dedicate bufg
 
 

嗨， 
我正在研究ADC 1252.我在这里附加了波形。
要从ADC读取数据，我正在编写VHDL代码。
我将通过将SCLK保持高电平同步5个DRDY周期来同步多个ADC。然后我将检测DRDY。
如果检测到i将生成SCLK以从ADC读取数据。
这个SCLK一代正常发生了30或40次。
然后这个SCLK将成为CLK。 
如果我使用内部时钟，那么SCLK一直在生成。
但我无法做同步。
感谢你，Mahesh Hegde。



以下为原文

Hi,
      I am working on ADC 1252. I have attached the waveforms here. To read the data from ADC i am writing VHDL code. I will synchronize the multiple ADC by helding SCLK high for 5 DRDY cycles.Then i will detect DRDY. If detects i will generate SCLK to read the data from ADC. This SCLK generation is happening properly for 30 or 40 times. Then this SCLK will become CLK.
      If i use internal clock then SCLK is generating all the time. But i am not able to do synchronization.
Thanks You in Advance,
Mahesh Hegde.

马赫什，
你没有让任何人轻易帮助你。
您对问题的描述缺乏细节。
您假设我们都是您的A / D转换器的专家，并且您没有提供可以搜索数据表的正确部件号。
对于读者而言，Mahesh正在使用的部分（我相信）是具有串行数据接口的TI低频24位A / D转换器。
制造商P / N是ADS1252U，数据表链接在这里。
ADC是delta-sigma器件。
其CLK输入用于对delta-sigma数据路径进行排序。
CLK是样本输出率的384倍。
最大CLK频率为16MHz。
串行数据时钟SCLK独立于系统CLK。
ADS1252U是5V器件，输入和输出逻辑电平与任何Xilinx 3.3V VCCO FPGA系列都不兼容。
在数据表中非常清楚地解释了同步多个A / D的过程，并且所涉及的频率很容易在基于FPGA的状态机的能力范围内，该状态机的时钟频率为32MHz或更高。
Mahesh，这是一个学校项目，这是一个商业项目，还是这个大项目的一个组成部分？
如果您对构建具有完整24位有效A / D转换的电路板感兴趣，电路板设计将需要经验丰富的电路板设计师的全部才能和技能。
一点点的邋iness或者捣蛋都会破坏任何接近24位有效分辨率的机会。
该设备的最大采样率约为40KHz。
如果您对数字化全频谱音频（20Hz-20KHz）感兴趣，即使使用异乎寻常的抗混叠滤波器，此转换器也会太慢。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Mahesh,
 
You have not made it easy for anyone to help you.  Your description of your problem is lacking detail.  You assume that we are all experts in your A/D converter, and you haven't provided a proper part number which can be searched for a datasheet.
 
For the reading audience, the part which Mahesh is using is (I believe) a TI low-frequency 24-bit A/D converter with serial data interface.  Manufacturer P/N is ADS1252U, and the datasheet link is here.
 
The ADC is a delta-sigma device.  Its CLK input is for sequencing the delta-sigma datapath.  The CLK is 384x the sample output rate.  Max CLK frequency is 16MHz.
 
The serial data clock, SCLK, is independent of the system CLK.
 
The ADS1252U is a 5V part, and input and output logic levels are incompatible with any of the Xilinx 3.3V VCCO FPGA families.
 
The process for synchronising multiple A/Ds is very clearly explained in the datasheet, and the frequencies involved are easily within the capabilities of a FPGA-based state machine clocked at 32MHz or higher.
 
Mahesh, is this a school project, is this a commercial project, or is this one component of a larger project?  If you are interested in building a board with full, 24-bit effective A/D conversion, the circuit board design will need the full talents and skills of a very experienced board designer.  The least bit of sloppiness or miscue will ruin any chances of attaining anywhere near 24-bit effective resolution.
 
The maximum sampling rate of this device is around 40KHz.  If you are interested in digitising full-spectrum audio (20Hz-20KHz), this converter is too slow, even with an exotic anti-aliasing filter.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

你好 
感谢你的回复。
我解决了这个问题。
感谢你，Mahesh Hegde。



以下为原文

Hi
   Thanks for all your replies. I solved the problem.
Thanks You in Advance,
Mahesh Hegde.