检查FPGA的FPGA功能和I/O引脚的方法

嗨Mahesh，
这种方法背后的情况是什么？
是在生产电路板后进行质量检查，还是在工作/客户部署后进行电路板健康监测？
我怀疑你的方法对上述任何一个都有益。
- 电路板制造商应具备专业的电路测试仪，以确保生产质量。
无需重新发明这个轮子。
- 增加电路板的复杂性和/或使用具有两倍I / O的更大设备会产生更多可能的故障点，如果故障发生在PC的接口引脚上，如何监控？
此外，如果测试只运行一次（例如上电后），然后电路板工作数小时或更长时间，那么就会出现故障（例如由于热变化），那么测试的优点是什么？
想想何时想要捕捉到什么样的错误。
以及测试之后或之间发生的事情。
这也有助于您确定测试可能需要哪种额外工具（环回电缆等）。
除了功能设计之外，或者你必须为它加载不同的位文件，它还会使你的测试必须有所不同。
有一个很好的综合 
Eilert
在原帖中查看解决方案



以下为原文

Hi Mahesh,
what is the scenario behind this approach?
Is it for quality inspection after production of the board, or is it for board health monitoring after deployment at the point of work/custumer?
 
I doubt that your approach is benefitial to any of the above.
- Board manufacturers should have professional in circuit testers to ensure production quality. No need to invent this wheel again.
- Increasing the complexity of a board and/or using a larger device with twice the I/Os  creates more possible points of failure, and how do you monitor it if the failure happens in your interface pins to the PC? Also, if the test runs just once (e.g. after power up) and then the board works for hours or longer, failures could appear just then (e.g. due to thermal changes) so what's the test good for?
 
Think about when you want to catch what kind of errors.
And also what's happening after or in between of tests.
This also helps you to determine what kind of extra tools (loopback cables etc.) might be required for your tests.
Also it makes some difference wether your tests have to be implemented besides the functional design or if you have to load a different bitfile for it.
 
Have a nice synthesis
   Eilert
View solution in original post

嗨Mahesh，
为了检查（您的设计的）内部功能，您可以构建一些BIST模块。
阅读集成电路部分 
http://en.wikipedia.org/wiki/Built-in_self-test
得到一个主意。
检查I / O是另一回事。
你要离开FPGA，需要在设备外部进行激励和响应控制。
在电路板生产期间，通常使用在线测试仪并使用IC的JTAG接口来检查连接和I / O驱动器。
如果您自己设计电路板，可以并行使用第二个FPGA，这样两个设备就可以相互检查。
但是这种方法也会变得复杂和昂贵。
另一种方法是在板外激发已经连接的硬件并寻找预期的返回信号。
（例如，在某些外部存储器上进行一些虚拟读/写操作。如果回读正确，则I / O驱动程序可以正常工作。）
这种方法更便宜，但非常特定于电路板，并且测试有时会受到限制，具体取决于所连接硬件的类型。
（例如，如何验证Txd输出是否有效？没有标准的返回路径。或者您将第二个I / O引脚用作感测Txd的输入。但是如果感测输入失败，而Txd工作正常怎么办？
只是增加了失败点？）
那么，你的目标是什么？
有一个很好的综合 
Eilert



以下为原文

Hi Mahesh,
for checking the internal function (of your design) you could build some BIST module.
Read the integrated circuits section of
   http://en.wikipedia.org/wiki/Built-in_self-test
to get an idea.
 
Checking the I/Os is another thing. There you are leaving the FPGA and need stimuli and response controll outside the device. During board production this is normally done using In-Circuit testers and using the JTAG interface of ICs for checking the connections and I/O drivers.
 
If you design your board yourself you could use something like a second FPGA in parallel so both devices can check each other. But this method would be kind of complicated and costly too.
Another method would be to stimulate the already attached hardware outside the board and look for expected return signals. (e.g. doing some dummy read/writes on some external memory. If the readback is correct, the I/O drivers work.)
This method is cheaper, but very board specific and the tests are sometimes limited depending on the kind of attached hardware. (e.g. how to verify that the Txd output works? There's no standard return path. Or you spend a second I/O pin as input to sense Txd. But what if the sense input fails, while Txd works fine? Much effort for nothing or just an increase of failure points?)
 
So, what's your goal in detail?
 
 
Have a nice synthesis
  Eilert
 
 

离开信号的常用方法是构建环回电缆进行测试。
然后你可以驱动信号并检查它们是否正确地循环回到有线电视
环回引脚。
-  Gabor
-  Gabor



以下为原文

A common approach to signals that go off board is to build a loop-back cable for testing.
Then you can drive signals out and check that they properly loop back to the cabled
loopback pin.
 
-- Gabor
-- Gabor

嗨，
感谢您的回复。我打算在没有连接任何环回电缆的情况下自我测试电路板。
正如你所说，我可以走这条路。
FPGA IO引脚1至50使用连接器从外部（使用环回连接器）连接到FPGA IO引脚51至100
加载FPGA文件
切换引脚1并检查引脚51状态
切换引脚2并检查引脚52状态
所有50个引脚都是一样的
结果显示在PC上显示的GUI中。
但我认为在更大的FPGA系列中使用环回电缆很困难（I / O引脚会更多，因此连接器尺寸也非常小）。
因为我应该看到连接器兼容性。
如果我开始兼容连接器以连接环回电缆，则电路板中的连接器数量将变得更多。
因此，电路板尺寸将再次增加。
有没有更好的方法来检查I / O引脚的I / O / Dameges之间的I / O功能/短路？
谢谢你，Mahesh Hegde



以下为原文

Hi,
Thanks for replies.I am planning to Selftest the board without connecting any loopback cable externally. As you suggested i can move in this path. 
 

•  FPGA IO pins 1 to 50 are connected to FPGA IO pins 51 to 100 externally(with loopback connector) using a connector
  
•  Load FPGA File
  
•  Toggle pin 1 and check pin 51 status
  
•  Toggle pin 2 and check pin 52 status
  
•  Same is done for all 50 pins
  
•  Results are displayed in GUI which is displaying on PC.
  

 But i think it's difficult to use loopback cable in larger families of FPGA (I/O pins will be more so connector size is also very small). because i should see connector compatibility. if i start doing compatibility to the connectors to connect loopback cable, number of connectors in the board will become more. So again board size will become increase.
Is there any better way to check the I/O functionality / short between I/O's / dameges of I/O pin?
  
Thanking You,
Mahesh Hegde

嗨Mahesh，
这种方法背后的情况是什么？
是在生产电路板后进行质量检查，还是在工作/客户部署后进行电路板健康监测？
我怀疑你的方法对上述任何一个都有益。
- 电路板制造商应具备专业的电路测试仪，以确保生产质量。
无需重新发明这个轮子。
- 增加电路板的复杂性和/或使用具有两倍I / O的更大设备会产生更多可能的故障点，如果故障发生在PC的接口引脚上，如何监控？
此外，如果测试只运行一次（例如上电后），然后电路板工作数小时或更长时间，那么就会出现故障（例如由于热变化），那么测试的优点是什么？
想想何时想要捕捉到什么样的错误。
以及测试之后或之间发生的事情。
这也有助于您确定测试可能需要哪种额外工具（环回电缆等）。
除了功能设计之外，或者你必须为它加载不同的位文件，它还会使你的测试必须有所不同。
有一个很好的综合 
Eilert



以下为原文

Hi Mahesh,
what is the scenario behind this approach?
Is it for quality inspection after production of the board, or is it for board health monitoring after deployment at the point of work/custumer?
 
I doubt that your approach is benefitial to any of the above.
- Board manufacturers should have professional in circuit testers to ensure production quality. No need to invent this wheel again.
- Increasing the complexity of a board and/or using a larger device with twice the I/Os  creates more possible points of failure, and how do you monitor it if the failure happens in your interface pins to the PC? Also, if the test runs just once (e.g. after power up) and then the board works for hours or longer, failures could appear just then (e.g. due to thermal changes) so what's the test good for?
 
Think about when you want to catch what kind of errors.
And also what's happening after or in between of tests.
This also helps you to determine what kind of extra tools (loopback cables etc.) might be required for your tests.
Also it makes some difference wether your tests have to be implemented besides the functional design or if you have to load a different bitfile for it.
 
Have a nice synthesis
   Eilert

嗨， 
谢谢你的回复。
我将使用Loopback电缆来测试FPGA的I / O引脚。
但有一点我怀疑是“由于某种原因导致2或3个I / O引脚出错。我可以在Selftest应用程序运行时显示此消息'此I / O不起作用'而不是显示'FPGA部分无法正常工作'
这非常困难吗？
谢谢你，Mahesh Hegde



以下为原文

Hi,
      Thank you for all your replies. I am going to use Loopback cable to test the I/O pins of FPGA. But one doubt i have is "2 or 3 I/O pins gone wrong because of some reason. Can i display this message while Selftest application is running 'This I/O's is not working' instead of displaying 'FPGA part is not working'. Is this very much difficult? 
Thanking You,
Mahesh Hegde

嗨Mahesh，
如果你能够在测试后以某种方式显示任何东西，根据某些条件选择结果字符串应该不会太复杂。
你甚至可以做些什么。
喜欢这个：
核心功能：确定 -  IO测试：失败
核心功能：失败 -  IO测试：好的
所以你在一个字符串中都有两个信息，只根据测试结果替换OK和Fail
有一个很好的综合 
Eilert



以下为原文

Hi Mahesh,
If you are able to display anything somehow after testing it should not bee too complicated to select the result string according to some conditions. You could even do sthg. like this:
Core Function: OK    -  IO Test: Fail
Core Function: Fail   -  IO Test: OK
 
So you have both infos in one string and only replace OK and Fail according to the test results
 
Have a nice synthesis
  Eilert

我在我的主板上使用xC6SLX100 fgpa。
PLL被锁定并且所有时钟都正确，但是没有发生位分配。
所有板载电压和电源电流都是正确的。
任何人都可以帮我确定问题是与fpga或某些董事会问题有关吗？



以下为原文

I am using xC6SLX100 fgpa on my board. PLL is getting locked and all the clocks are coming correct but the bit allignment is not happening. All the on-board voltages and supply currents are coming correct. Can anyone help me in identifying that whether the problem is with fpga or some board issue?

@ sg1在线程关闭后创建一个新帖子（如果问题类似于讨论的线程，你可以指向线程）。
这个设计在模拟中有效吗？
如果是，请插入chipcope并检查。
-Pratham ------------------------------------------------
----------------------------------------------请注意 - 请
如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K-
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以下为原文

@sg1 Always create a new post once thread is closed (you can point thread if problem is similar to thread discussed).
 
Is this design working in simulation? If yes insert chipscope and check.
-Pratham

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嗨Pratham，
问题解决了。
Bufio2正在生成DIV clk，因此我们在没有它的情况下生成它并且它起作用。
谢谢顺便说一句



以下为原文

Hi Pratham,
 
The problem got solved. Bufio2 was generating the DIV clk, so we generated it without it and it worked.
Thanks btw