怎么将1PPS从GPS接收器连接到FPGA I/O引脚之一

输入InPulse;
reg InPulseQ;
reg InPulseQQ;
电线RisingEdgeDetected;
总是@（posedge Clock） 
开始 

InPulseQ 以下为原文

input  InPulse;
 
reg InPulseQ;
reg InPulseQQ;
 
wire RisingEdgeDetected;
 
always @ ( posedge Clock)
  begin
    InPulseQ  <= InPulse;   // register for input synchronization
    InPulseQQ  <=  InPulseQ;  // one clock cycle delay
  end
 
assign RisingEdgeDetected = InPulseQ && ~InPulseQQ;  // single cycle pulse when rising edge detected
 
// NOTE:  Clock freq must be high enough to capture InPulse;
// in UCF or Planahead, specify pin number (and IO standard) for InPulse input pin
 
 
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README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

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非常感谢
DCM时钟和1 pps不同步。
在那种情况下，始终使用块代码

InPulseQ 以下为原文

Many Thanks
 
DCM clock and 1 pps are not synchronised. In that case in the always block  code
 
InPulseQ  <= InPulse ,
 
InPulse is not necessary be the rising edge of 1 pps .
 
Also I can't follow one clock cycle time delay in the code
 
 
I am here with explaining the problem more detail
 
FPGA has free running counter which is triggered with rising edge clock of 100 MHz clock from DCM. When the counter reaches a certain value ,  I/O pin in which 1 pps is connected is opened and will wait for the rising edge of  1 pps. Counter value is recorded in buffer once rising edge of 1 pps pulse is detected in th I/O pin.
 
 
Thanks and Regards
 
Faisal