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嗨,我在实施过程中面临以下实施错误。
当我将sdc中的时钟周期设置为18ns时,可以成功完成实现,而不会出现任何时序/网络错误。 但如果时钟周期限制在15ns,vivado将在下面生成错误消息。 我附上整个日志文件和屏幕截图供参考。 任何人都可以帮助我找出这个错误的根本原因以及它与时钟约束变化的关系吗? 提前致谢。 错误:[放置30-487]无法遵守实例到设备中的包装。 请分析您的设计,以确定是否可以减少LUT,FF和/或控制集的数量。实例数:触发器:在考虑的设计区域中为217018,在设备中可用2443200(注意:每个切片只能 容纳1个独特的控制集,因此无法打包FF以完全填充每个切片)Luts:426661(组合)426661(总计)在设计区域内,1221600可用于deviceControl集:71574 in device未放置的实例需要79296个切片但只有72012个 设备中有305400个切片可用,因为其他切片可能被放置的实例占用或被排除放置阻止。 runme.log 128 KB 以上来自于谷歌翻译 以下为原文 Hi, I am facing following implementation error during implementation. When I set the clock period in sdc to be 18ns, the implementation can be completed successfully without any timing/nets error. But if the clock period is constrained to 15ns, vivado will generate the error message below. I am attaching the whole log file and a screen shot for reference. Can anyone help me to figure the underlying root cause of this error and how it is related to the clock constraint change? Thanks in advance. ERROR: [Place 30-487] The packing of instances into the device could not be obeyed. Please analyze your design to determine if the number of LUTs, FFs, and/or control sets can be reduced. Number of instances: Flip flops: 217018 in the design area under consideration, 2443200 available in the device (NOTE: each slice can only accommodate 1 unique control set so FFs cannot be packed to fully fill every slice) Luts: 426661(combined) 426661 (total) in design area under consideration, 1221600 available in device Control sets: 71574 in device The unplaced instances require 79296 slices but only 72012 out of 305400 slices in the device are available, because others may be occupied by placed instances or blocked by exclude placement. runme.log 128 KB |
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你好@ pine_king
尝试以牺牲运行时为代价尝试放置更高的工作量,请使用以下tcl命令,将limit的值设置为2000或更多.set_param place.sliceLegEffortLimit limit 在synthes.dcp和opt.dcp文件上运行命令:report_control_sets以查看控件集差异。 谢谢, 维奈 -------------------------------------------------- ------------------------------------------您是否尝试在Google中输入问题? ? 如果没有,你应该在发布之前。 此外,MARK这是一个答案,以防它有助于解决您的查询/问题。给予帮助您找到解决方案的帖子。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Hi @pine_king Try attempting placement at higher effort levels at the expense of runtime, please use the following tcl command, setting the value of limit to 2000 or more. set_param place.sliceLegEffortLimit limit Run the command: report_control_sets on synthesized.dcp and opt.dcp files to see control sets differences. Thanks, Vinay -------------------------------------------------------------------------------------------- Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution.View solution in original post |
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你好@ pine_king
从错误消息中可以清楚地看出,由于许多控件集,该工具无法放置所有实例。 请参阅控制集报告并尝试减少设计中的控制集。 您将在impl_1目录中找到名为xxxxxx_control_sets_placed.rpt的控制集报告 谢谢, 维奈 -------------------------------------------------- ------------------------------------------您是否尝试在Google中输入问题? ? 如果没有,你应该在发布之前。 此外,MARK这是一个答案,以防它有助于解决您的查询/问题。给予帮助您找到解决方案的帖子。 以上来自于谷歌翻译 以下为原文 Hi @pine_king From the error message, it is clear that the tool is unable to place all instances because of many control sets. See control set report and try reducing the control sets in the design. You will find the control set report in impl_1 directory with name xxxxxx_control_sets_placed.rpt Thanks, Vinay -------------------------------------------------------------------------------------------- Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution. |
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嗨@vuppala,
感谢您的答复:) 我检查了impl_1目录但没有找到报告文件。 也许在vivado错误出现之前没有调用thereport_control_sets命令? 任何想法,我可以在vivado错误之前得到报告? 您的解释非常合理,我会在看到详细报告时尝试优化设计。 再次感谢。 以上来自于谷歌翻译 以下为原文 Hi @vuppala, Thanks for your response:) I have checked the impl_1 directory but have not found the report file. Maybe the report_control_sets command is not invoked before vivado errorred out? Any idea I can get the report before vivado error out? Your explanation is very resonable, I will try to optimize the design when I can see the detailed report. Thanks again. |
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另一个问题,当时钟被限制在20ns时怎么样,错误没有出现?
实施的哪一步将导致控制集#增加? 以上来自于谷歌翻译 以下为原文 Another question, how come when the clock is constrained to 20ns, the error does not show up? Which step of the implementation will lead to the control set# being increased? |
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检查此ARs https://www.xilinx.com/support/answers/54958.html
谢谢和RegardsBalkrishan ----------------------------------------------- ---------------------------------------------请将帖子标记为 一个答案“接受为解决方案”,以防它有助于解决您的查询。如果一个帖子引导到解决方案,请给予赞誉。 以上来自于谷歌翻译 以下为原文 check this ARs https://www.xilinx.com/support/answers/54958.htmlThanks and Regards Balkrishan -------------------------------------------------------------------------------------------- Please mark the post as an answer "Accept as solution" in case it helped resolve your query. Give kudos in case a post in case it guided to the solution. |
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你好@ pine_king
尝试以牺牲运行时为代价尝试放置更高的工作量,请使用以下tcl命令,将limit的值设置为2000或更多.set_param place.sliceLegEffortLimit limit 在synthes.dcp和opt.dcp文件上运行命令:report_control_sets以查看控件集差异。 谢谢, 维奈 -------------------------------------------------- ------------------------------------------您是否尝试在Google中输入问题? ? 如果没有,你应该在发布之前。 此外,MARK这是一个答案,以防它有助于解决您的查询/问题。给予帮助您找到解决方案的帖子。 以上来自于谷歌翻译 以下为原文 Hi @pine_king Try attempting placement at higher effort levels at the expense of runtime, please use the following tcl command, setting the value of limit to 2000 or more. set_param place.sliceLegEffortLimit limit Run the command: report_control_sets on synthesized.dcp and opt.dcp files to see control sets differences. Thanks, Vinay -------------------------------------------------------------------------------------------- Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution. |
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嗨Balkrishan,AR是提供信息的,但它只涉及合成阶段,而不是实施...谢谢,宋
以上来自于谷歌翻译 以下为原文 Hi Balkrishan, The AR is informative but it is related to only synthesis phase, not implementation... Thanks, Song |
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嗨Vinay,这真的很有帮助,谢谢。
我已经找到了为什么会识别出大量的控制装置,并随着项目而移动。谢谢,宋 以上来自于谷歌翻译 以下为原文 Hi Vinay, This really helps, thanks. I have found out why the huge number of control set is identified and will move with the project. Thanks, Song |
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嗨@ pine_king,
我知道这是一个老帖子。 但是,我正在试试我的运气,因为我面临类似的问题。 您是如何设法减少布局器成功工作的控制集的? 对我来说,即使增加了布局工作量限制或更改时钟频率,布局器仍会显示错误。 谢谢, 酒窝 以上来自于谷歌翻译 以下为原文 Hi @pine_king, I know this is an old post. However, I am trying my luck here since I am facing a similar issue. How did you manage to reduce the control sets for the placer to work successfully? For me, the placer continues to show errors even after increasing the placer effort limit or changing the clock frequency. Thanks, Dimple |
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