设计有助于Vivado的xc7v2000芯片收到错误

@ doka978，
您在哪个位置锁定BUFG？
您的设计中有多少个BUFG？
由于您使用的是SSI设备，请参阅http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-methodology.pdf的第192页“SSI设备的附加时钟注意事项”。
--Syed
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以下为原文

@doka978,
 
At which location are you locking the BUFG?  How many BUFG are present in your design? 
 
Since you are using SSI device, Refer to page-192 "Additional Clocking Considerations for SSI Devices" of  http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-methodology.pdf
 
--Syed
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@ doka978，
您在哪个位置锁定BUFG？
您的设计中有多少个BUFG？
由于您使用的是SSI设备，请参阅http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-methodology.pdf的第192页“SSI设备的附加时钟注意事项”。
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
--------------------------------------------------
-------------------



以下为原文

@doka978,
 
At which location are you locking the BUFG?  How many BUFG are present in your design? 
 
Since you are using SSI device, Refer to page-192 "Additional Clocking Considerations for SSI Devices" of  http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-methodology.pdf
 
--Syed
---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
---------------------------------------------------------------------------------------------

嗨，
根据第一条错误消息，您的理解是正确的，区域缓冲区不合适，需要转移到BUFG。
现在，当你搬到BUFG时，它是如何连接的？
使用了多少％？
请参阅http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-methodology.pdf中的“SSI设备的附加时钟注意事项”第138页。
谢谢，佳日



以下为原文

Hi,
 
As per 1st error message your understanding is correct that regional buffer is not suitable and need to move to BUFG.
Now as you moved to BUFG, how exactly it is being connected? How much % is utilized?
 
Refer to "Additional Clocking considerations for SSI devices" page-138 of http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-methodology.pdf
 
Thanks,
Yash
 

@syedz
>>你在哪个位置锁定BUFG？
您的设计中有多少个BUFG？
除引脚位置和时钟外没有任何限制
post_synth_util.rpt：
5.时钟-----------
+ ------------ + ------ + ------- + ----------- + ------- + |
网站类型|
二手|
固定|
可用|
Util％| + ------------ + ------ + ------- + ----------- + ------
-  + |
BUFGCTRL |
53 |
0 |
128 |
41.4 ||
BUFIO |
0 |
0 |
96 |
0.00 ||
MMCME2_ADV |
0 |
0 |
24 |
0.00 ||
PLLE2_ADV |
1 |
0 |
24 |
4.17 ||
BUFMRCE |
0 |
0 |
48 |
0.00 ||
BUFHCE |
0 |
0 |
288 |
0.00 ||
BUFR |
0 |
0 |
96 |
0.00 | + ------------ + ------ + ------- + ----------- + -------
+



以下为原文

@syedz
>> At which location are you locking the BUFG?  How many BUFG are present in your design? 
 
dont have any constraints except pin location and clocks
 
post_synth_util.rpt:
 
5. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL   | 53 | 0 | 128 | 41.4 |
| BUFIO      | 0  | 0 | 96  | 0.00 |
| MMCME2_ADV | 0  | 0 | 24  | 0.00 |
| PLLE2_ADV  | 1  | 0 | 24  | 4.17 |
| BUFMRCE    | 0  | 0 | 48  | 0.00 |
| BUFHCE     | 0  | 0 | 288 | 0.00 |
| BUFR       | 0  | 0 | 96  | 0.00 |
+------------+------+-------+-----------+-------+

可能我选择了错误的GCLK引脚用于时钟输入？
我使用xc7v2000tfhg1761-2并将时钟源连接到pinAK34 [IO_L12P_T1_MRCC_14]



以下为原文

Probably I choice wrong GCLK pin for clock input?
 
I use xc7v2000tfhg1761-2 and connect clock source to pin AK34 [IO_L12P_T1_MRCC_14]

我通过手动重写RTL以解决某些代码中使用的BUFG来解决这个问题。
谢谢大家解释问题的根源



以下为原文

I solved this issue by manually rewriting RTL to derceasing of BUFG used in some code.
 
Thanks all for explanation the root of issue

我遇到了同样的问题。
你是如何重写rtl来减少使用的bufg的？
我还有很多可以使用的bufg。
我应该在我的设计中实例化更多的bufg吗？
感谢名单。



以下为原文

i encountered the same issue. how did you rewrite rtl to reduce bufg used?
i still have plenty of bufg that i can use. shall i instantiate more bufg in my design?
 
thanx.